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M16C/6S Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0014-0400 Rev.4.00 Aug 05, 2005
Overview
The M16C/6S group are highly integrated single-chip microcomputers with PLC (Power Line Communication) modem core and AFE (Analog Front End) in a 64-pin plastic molded LQFP package, which incorporates IT800 PLC modem technology developed by Yitran Communications Ltd. M16C/60 Series CPU core enables a high level of code efficiency and high-speed operation. In addition, the implementation of Yitran's patented DCSK (Differential Code Shift Keying) spread spectrum modulation technique in the IT800 modem core enables extremely robust communication over the existing electrical wiring, with data rates up to 7.5Kbps. The M16C/6S complies with worldwide regulations (FCC part 15, ARIB and CENELEC bands) and is suitable for a variety of narrowband applications like AMR (Automatic Meter Reading) and home networking.
Applications
Power Line Communication
------Table of Contents-----Overview ......................................................... 1 Memory ......................................................... 10 Central Processing Unit (CPU) ..................... 11 SFR ............................................................... 13 Reset ............................................................. 19 Processor Mode ............................................ 23 Clock Generation Circuit ............................... 27 Protection ...................................................... 46 Interrupts ....................................................... 47 Watchdog Timer ............................................ 66 DMAC ........................................................... 68 Timers ........................................................... 78 Timer A ...................................................... 79 Serial I/O ....................................................... 92 Clock Synchronous serial I/O Mode ........ 101 UART Mode ............................................. 109 Special Mode ........................................... 117 SI/O3 and SI/O4 ...................................... 132 Programmable I/O Ports ............................. 137 Electrical Characteristics ............................. 149 Flash Memory Version ................................ 160 IT800AFE (Analog Front End) .................... 183 Appendix ..................................................... 188
Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition.
Rev.4.00 Aug 05, 2005 REJ03B0014-0400
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M16C/6S Group
Overview
Performance Outline
Table 1.1.1 lists performance outline of M16C/6S group. Table 1.1.1. Performance outline of M16C/6S group CPU Item Number of basic instructions Minimum Instruction Execution time Operation Mode Memory Space Memory Capacity ROM RAM Port Multifunction Timer Serial I/O Performance 91 instructions 65.1 ns (f(BCLK)= 15.36MHZ, VCC= 3.0V to 3.6V)
Single-chip mode 1M Byte 96K Byte 24K Byte Peripheral Input/Output : 21 pins, Input : 1 pin Function Timer A : 16 bits x 5 channels, 2 channels Clock synchronous, UART, I2C bus(1), 1 channel UART, I2C bus(1), 2 channels Clock synchronous(*) (*) 1 channel is internally connected to IT800 DMAC 2 channels Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt 21 internal and 3 external sources, 4 software sources, 7 levels Clock Generation Circuit 2 circuits Main clock generation circuit with PLL synthesizer (*), On-chip oscillator, (*) This circuit contains a built-in feedback resister. Electrical Power supply voltage 3.0V to 3.6V Characteristics Power Consumption 70mA (VCC= VCCA= 3.3V, f(XIN)= 5.12MHz) Flash memory Program/Erase Supply Voltage 3.0V to 3.6V (Topr= 0 to 60C) Version Program and Erase Endurance 100 times or 1,000 times (2) Power consumption 70mA (VCC= VCCA= 3.3V, f(XIN)= 5.12MHz) Operating Ambient Temperature -20 to 85C -40 to 85C (2) Package 64-pin plastic mold LQFP Notes: 1. I2C Bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. See Table 1.1.4 Product code for increased program/erase cycle version, and version of expanded operating ambient temperature.
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M16C/6S Group
IT800 PHY performance outline of M16C/6S group.
The IT800 PHY is a PLC optimized Physical Layer (PHY) which consists of IT800 modem core and internal AFE (Analog Front End). The implementation of Yitran's patented DCSK spread spectrum modulation technique in the IT800 modem core enables extremely robust communication over the existing electrical wiring, with data rates up to 7.5Kbps. In addition to the inherent interference immunity provided by the DCSK modulation, the IT800 PHY utilizes several mechanisms for enhanced communication robustness, such as forward short block soft decoding error correction algorithm and special synchronization algorithms. The IT800PHY communicates M16C core with clock synchronous serial I/O, interrupt and input/output ports in M16C/6S (Note). M16C/6S requires external AFE. Table 1.1.2 lists IT800 PHY performance outline of M16C/6S group. Table 1.1.2. IT800 PHY performance outline of M16C/6S group Item Performance Features High immunity to signal fading, various noise characteristics, impedance modulation and phase/frequency distortion High in-phase and cross-phase reliability Modulation Technique DCSK (Differential Code Shift Keying)* *Yitran patented modulation technique Error Correction Forward short-block soft decoding error correction mechanism, CRC-16 Complies with W/W Regulations FCC, ARIB, EN50065-1-CENELEC Data Rate & FCC & ARIB 120-400 KHz Frequency Band 7.5Kbps Standard Mode (SM) 5.0Kbps Robust Mode (RM) 1.25Kbps Extremely Robust Mode (ERM) CENELEC A-Band (Outdoor): 20-80 KHz B-Band (Indoor): 95-125 KHz 2.5 Kbps Robust Mode (RM) 0.625Kbps Extremely Robust Mode (ERM) Internal AFE 10bit-D/A converter, preamp, 1bit-A/D converter x 3 channels Note: Direct operation of IT800 PHY is not recommended. Since the Layer 2 (DLL) handles the channel access procedure, using the IT800DLL as such assures coexistence with other IT800 technology based products, regardless of the vendor, protocol and the application. There is NO such coexistence if the device is used in direct operation of IT800 PHY. Note that the coexistence here is not with other technologies but with other IT800 technology based products. As for details, please refer to the next section and Appendix.
About Firmware
Renesas recommends IT800DLL as a Data Link Layer (DLL) of M16C/6S group. The IT800 DLL is a PLC optimized DLL especially for the products based on Yitran's IT800 technology. For availability of IT800DLL, please contact Renesas technical support representative. For more details about the IT800DLL advantages, please refer to Appendix. Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 3 of 190
Block Diagram of Chip
M16C/6S Group
M16C Core
P11 TEST_A TS P41
IT800 Modem Core Internal AFE
Line driver
M16C/60 series 16-bit CPU core
register
R2 R3 A1 TS 10 SO P10 TEST_C IOUTC Buffer 10bit D/A Re xt IOUT Buffer
1
Port P1
8
Port P6
5
Port P7
5
Port P8
Port P85
3
Port P9
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Line coupling
Preamplifier PRE_INP PRE_INN VREF P95/CLK4 P96/SOUT4 P97/SIN4 P40 TXnRX CLR nPHY_RES nCD1 1bit-A/D x 3 nCD0 nINT
OPAMP
R0H R1H
R0L R1L
Program Counter
A0 FB SB
PC
Vector table
Stac P k ointer
INTB
USP ISP
Multiplier
Flag register
Block Diagram and PLC application Outline
Figure 1.1.1. Block Diagram of Chip and PLC application Outline
Inner Ports
DCLK DI DO
BUFFER OPAMP
Figure 1.1.1 is a block diagram of the M16C/6S group and PLC application Outline.
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PRE_BOUT P42 P56 P54 P53 P82/INT0 SI1
Compar ator
FLG
Internal Peripherals
Clock synchronous serial I/O (8bits 2channels)
UART or Clock synchronous serial I/O (8bits 3channels) VccA VssA CH1_INP AMP1_OUT AMP1_IN
Watchdog timer (15bits)
Filters
Timer (16bits) Output (TimerA) 5
BPF 100 to 200KHz CH1_INN FB1 CH2_INP AMP2_OUT AMP2_IN
DMA C (2channels) EXTCLK 15.36MHz
System clock generator
Memory
OPAMP
BPF VREF CH2_INN FB2 CH3_INP AMP3_OUT AMP3_IN
OPAMP
ROM
RAM
SI2
Compar ator
200 to 300KHz
XIN SI3 CLK_IN 46.08MHz
BPF
Compar ator
5.12MHz
PLL module
300 to 400KHz CH3_INN FB3
XOUT
Overview
M16C/6S Group
Overview
Product List
Tables 1.1.3 list the M16C/6S group product and Figure 1.1.2 shows the type numbers, memory sizes and packages. Table 1.1.3. Product List (1)
Type No. M306S0FAGP M306S0FA-XXXGP ROM capacity 96K bytes 96K bytes RAM capacity 24K bytes 24K bytes Package type PLQP0064KB-A (64P6Q-A) PLQP0064KB-A (64P6Q-A) Remarks Flash Memory version Flash Memory version with middleware August 2005
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M16C/6S Group
Overview
Type No.
M306S 0 F A -
X X X G P - U5
Product code See Table Product code Package type: GP : Package 64P6Q-A
ROM No.
ROM capacity: A: 96K bytes Memory type: F: Flash memory version
Shows RAM capacity, pin count, etc (The value itself has no specific meaning) M16C/6S Group M16C Family
Note. Simple Control protocol is developed by Microcomputer Corporation for Home Network.
Figure 1.1.2. Type No., Memory Size, and Package
Table 1.1.4. Product Code Internal ROM Block (0, 1, 2, 3) Product Code Package E/W cycles Temperature range Microcomputer operating temperature -40C to 85C -20C to 85C -40C to 85C -20C to 85C
U3 (D) U5 LEAD free U7 (D) U9 (D) (D): under development
100 0C to 60C 1,000
XXXXXXX 306S0FA U9 YITRAN IT800
Data Code (7 digits)
indicates manufacturing management code
Product Name and Product Code 306S0FA U9 indicates M306S0FAGP indicates product code (see Table 1.1.4) U5 has no product code marking This indicates using Yitran's IT800 technology
Figure 1.1.3. Marking (Top View) Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 6 of 190
M16C/6S Group
Overview
Pin Configuration
Figures 1.1.4 show the pin configurations (top view).
PIN CONFIGURATION (top view)
VCCA PRE_INP PRE_INN PRE_BOUT VCC25 XOUT XIN IFLT VSS P85 P84/INT2 P76/TA3OUT P81/TA4IN P74/TA2OUT P83/INT1 P62/RXD0/SCL0
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
CNVSS VSSA VREF VDCCN AMP1_IN AMP1_OUT AMP2_OUT AMP2_IN AMP3_IN AMP3_OUT CH3_INP CH3_INN FB3 CH2_INP CH2_INN FB2
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
M16C/6S YITRAN IT800
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
P63/TXD0/SDA0 TS P61/CLK0 P73/CTS2/RTS2/TA1IN P60/CTS0/RTS0 P66/RXD1/SCL1 P90/CLK3 P64/CTS1/RTS1/CLKS1 P91/SIN3 P67/TXD1/SDA1 P92/SOUT3 P65/CLK1 RESET P70/TXD2/SDA2/TA0OUT(Note) P71/RXD2/SCL2/TA0IN VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Figure 1.1.4. Pin Configuration (Top View)
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CH1_INP CH1_INN FB1 VCCA VSSA IOUTC IOUT REXT GND/TST VCC25 VCC NC3 NC2 NC1 P15/INT3 P80/TA4OUT
Package: PLQP0064KB-A (64P6Q-A)
Note: P70 is N channel open-drain output pins.
M16C/6S Group
Overview
Table 1.1.4 Pin Description (1)
Pin name VCC, VSS CNVSS RESET XIN XOUT VCCA Signal name Power supply input CNVSS Reset input Clock input I/O type Function Apply 3.0V to 3.6V to the VCC pin. Apply 0V to the VSS pin. This is a pin for changing flash memory mode. Usually, connect to VSS. "L" on this input resets the microcomputer. I/O pins for the main clock generation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT (3). To use the external clock, input the clock from XIN and leave XOUT open. This pin is a power supply input of analog circuit. Connect to VCC.
Input Input Input
Clock output Output
Analog power supply input VSSA Analog power This pin is a power supply input of analog circuit. Connect to VSS. supply input GND/TST Input for test Input This is input pin for test. Connect to VSS. P15 Input/output This is an 1-bit I/O port equivalent to P6. By choosing by the program, I/O port P1 it functions as an input pin of INT interrupt. VCC25 Power supply It is the 2.5V power supply pin which is carrying out internal generating. Connect VCC25 two pins each other and add stabilization capacity. Input/output This is the 8-bit I/O port of CMOS. It has a direction register for choosing I/O, and is P60 to P67 I/O port P6 made for every pin in an input port or an output port. An input port can choose the existence of pull-up resistance in a 4-bit unit by the program. It functions as an I/O pin of what is chosen by the program which are therefore UART0 and UART1. I/O port P7 Input/output It is an I/O port with a function equivalent to P6 (however, P70 N channel open-drain P70, P71, output). By choosing by the program, it functions as an I/O pin of timers A0 to A3. P73, P74, Moreover, P70 to P73 function also as an I/O pin of UART2. P76 P80, P81, I/O port P8 Input/output P80, P81, P83, and P84 are I/O ports with a function equivalent to P6. By choosing by the program, P80 to P81 function as an I/O pin of timer A4, P83, P84, and P83 to P84 functions as an input pin of INT interruption. P85 Input port P85 P90 to P92 I/O port P9 TS P10 P11 P40 Input P85 is a port with the common use only for inputs. Pull-up resistance cannot set up this pin. This pin must be pulled-up externally to Vcc, and be fixed to "H".
P41
P42
P53
P54
P56
P82
P95
P96
P97
Input/output It is an I/O port with a function equivalent to P6. It functions as an I/O pin of SILO3 by choosing by the program. Output port Output This is the pin with which IT800 controls ON/OFF of an output to the external TS transmission AMP at the time of power line communication. Inner port P10 keep Input Port for IT800 Testing. Please set Direction Register PD1_0 "0" for keeping Input. Inner port P11 keep Input Port for AFE Testing. Please set Direction Register PD1_1 "0" for keeping Input. Output to Inner port I/O Port for communication between M16C Core and IT800 Modem. Please set IT800 P40 Direction Register PD4_0 "1" to Output a signal to IT800. The output signal is connected to TXnRX of IT800 inside of chip. Input from I/O Port for communication between M16C Core and IT800 Modem (Note.1). Inner port IT800 P41 Please set Direction Register PD4_1 "0" to Input a signal from IT800. The TS signal is input from IT800 inside of chip. Output to Inner port I/O Port for communication between M16C Core and IT800 Modem. Please set IT800 P42 Direction Register PD4_2 "1" to Output a signal to IT800. The output signal is connected to CLR of IT800 inside of chip. Input from I/O Port for communication between M16C Core and IT800 Modem (Note.1). Inner port IT800 P53 Please set Direction Register PD5_3 "0" to Input a signal from IT800. The nCD0 signal is input from IT800 inside of chip. Input from I/O Port for communication between M16C Core and IT800 Modem (Note.1). Inner port IT800 P54 Please set Direction Register PD5_4 "0" to Input a signal from IT800. The nCD1 signal is input from IT800 inside of chip. Output to Inner port I/O Port for communication between M16C Core and IT800 Modem. Please set IT800 P56 Direction Register PD5_6 "1" to Output a signal to IT800. The output signal is connected to nPHY_RES of IT800 inside of chip. Input from I/O Port for communication between M16C Core and IT800 Modem (Note.1). Inner port IT800 P82 nINT signal of IT800 is connected to this port inside of chip for carrying out Interrupt function by software. Output to Inner port I/O Port for communication between M16C Core and IT800 Modem. This port is IT800 P95 connected to DCLK signal of IT800 inside of chip as SILO4 CLK4 functional Output port by choosing by the program. Output to Inner port I/O Port for communication between M16C Core and IT800 Modem. This port is IT800 P96 connected to DI signal of IT800 inside of chip as SILO4 SOUT4 functional Output port by choosing by the program. Input from I/O Port for communication between M16C Core and IT800 Modem. This port is Inner port IT800 P97 connected to DI signal of IT800 inside of chip as SILO4 SOUT4 functional Input port by choosing by the program.
NOTES: 1. In case of Direction Register "1", any signal is not output from M16C to assigned signal of IT800 . Refer to Programmable I/O Ports pages. 2. Ask the oscillator maker the oscillation characteristic. Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 8 of 190
M16C/6S Group
Overview
Table 1.1.5 Pin Description (2) (Analog pin)
Pin name PRE-BOUT PRE-INN PRE-INP VREF VDCCN AMP1-IN AMP1-OUT AMP2-IN AMP2-OUT AMP3-IN AMP3-OUT CHI-INP CHI-INN FB1 CH2-INP CH2-INN FB2 CH3-INP CH3-INN FB3 IOUTC IOUT REXT IFLT I/O type Output Input Input Input Input Input Output Input Output Input Output Input Input Output Input Input Output Input Input Output Output Output Input Input This is a pre-amp buffer output. This is a pre-amp differential signal input. This is a pre-amp differential signal input. This is the reference voltage input of amplifier common to channels 1, 2, and 3. This is a pin for a test. Usually, please carry out a pull-up. This is a channel 1 amplifier input. This is a channel 1 amplifier output. This is a channel 2 amplifier input. This is a channel 2 amplifier output. This is a channel 3 amplifier input. This is a channel 3 amplifier output. This is a channel 1 comparator differential input. This is a channel 1 comparator differential input. This is a channel 1 comparator feedback output. This is a channel 2 comparator differential input. This is a channel 2 comparator differential input. This is a channel 2 comparator feedback output. This is a channel 3 comparator differential input. This is a channel 3 comparator differential input. This is a channel 3 comparator feedback output. This is the differential current output of DAC. This is the differential current output of DAC. This is for external reference resistor of DAC. This is the pin for low path filters of PLL. Function
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M16C/6S Group
Memory
Memory
Figure 1.2.1 is a memory map of the M16C/6S group. The address space extends the 1M bytes from address 0000016 to FFFFF16. The internal ROM is allocated in a lower address direction beginning with address FFFFF16. For example, a 96-Kbyte internal ROM is allocated to the addresses from E800016 to FFFFF16. The fixed interrupt vector table is allocated to the addresses from FFFDC16 to FFFFF16. Therefore, store the start address of each interrupt routine here. The internal RAM is allocated in an upper address direction beginning with address 0040016. For example, a 24-Kbytes internal RAM is allocated to the addresses from 0040016 to 063FF16. In addition to storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated. The SRF is allocated to the addresses from 0000016 to 003FF16. Peripheral function control registers are located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be used by users. The special page vector table is allocated to the addresses from FFE0016 to FFFDB16. This vector is used by the JMPS or JSRS instruction. For details, refer to the "M16C/60 and M16C/20 Series Software Manual."
0000016 SFR 0040016 Internal RAM XXXXX16
Internal RAM Size 24K bytes Address XXXXX16 063FF16 Size 96K bytes Internal ROM Address YYYYY16 E800016
FFE0016
Special page vector table
Can not Use
FFFDC16
Undefined instruction
Overflow
BRK instruction Address match Single step Watchdog timer DBC Reserved Reset
YYYYY16
Internal ROM
FFFFF16 FFFFF16
Note 1: Shown here is a memory map for the case where the PM10 bit in the PM1 register is "1" and the PM13 bit in the PM1 register is "1".
Figure 1.2.1. Memory Map
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M16C/6S Group
Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 1.3.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks.
b31 b15 b8 b7 b0
R2 R3
R0H(R0's high bits) R0L(R0's low bits) R1H(R1's high bits)R1L(R1's low bits) R2 R3 A0 A1 FB Address registers (Note) Frame base registers (Note)
b0
Data registers (Note)
b19
b15
INTBH
INTBL
Interrupt table register
The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.
b19 b0
PC
b15 b0
Program counter
USP ISP SB
b15 b0
User stack pointer Interrupt stack pointer Static base register
FLG
b15 b8 b7 b0
Flag register
IPL
U I OB SZ DC
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area
Note: These registers comprise a register bank. There are two register banks.
Figure 1.3.1. Central Processing Unit Register
(1) Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32bit data register (R2R0). R3R1 is the same as R2R0.
(2) Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 11 of 190
M16C/6S Group
Central Processing Unit (CPU)
(3) Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
(4) Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
(5) Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
(6) User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
(7) Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
(8) Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status. * Carry Flag (C Flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. * Debug Flag (D Flag) The D flag is used exclusively for debugging purpose. During normal use, it must be set to "0". * Zero Flag (Z Flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, it is "0". * Sign Flag (S Flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, it is "0". * Register Bank Select Flag (B Flag) Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1". * Overflow Flag (O Flag) This flag is set to "1" when the operation resulted in an overflow; otherwise, it is "0". * Interrupt Enable Flag (I Flag) This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is "0", and are enabled when the I flag is "1". The I flag is cleared to "0" when the interrupt request is accepted. * Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is "0"; USP is selected when the U flag is "1". The U flag is cleared to "0" when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. * Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt is enabled. * Reserved Area When write to this bit, write "0". When read, its content is indeterminate.
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M16C/6S Group
SFR
SFR
Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
Register
Symbol
After reset
Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Address match interrupt enable register Protect register Oscillation stop detection register Watchdog timer start register Watchdog timer control register Address match interrupt register 0
(Note 2)
PM0 PM1 CM0 CM1 AIER PRCR
000000002(CNVSS pin is "L")
000010002 010010002 001000002 XXXXXX002 XX0000002 0000X0002 ??16 00??????2 0016 0016 X016 0016 0016 X016
(Note 3)
CM2 WDTS WDC RMAD0
Address match interrupt register 1
RMAD1
Processor mode register 2 DMA0 source pointer
PM2 SAR0
XXX000002 ??16 ??16 X?16 ??16 ??16 X?16 ??16 ??16
DMA0 destination pointer
DAR0
DMA0 transfer counter
TCR0
DMA0 control register
DM0CON
00000?002
DMA1 source pointer
SAR1
??16 ??16 X?16 ??16 ??16 X?16 ??16 ??16
DMA1 destination pointer
DAR1
DMA1 transfer counter
TCR1
DMA1 control register
DM1CON
00000?002
Note 1: The blank areas are reserved and cannot be used by users. Note 2: The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset. Note 3: The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset. X : Nothing is mapped to this bit ? : Undefined
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M16C/6S Group
SFR
Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16
Register
Symbol
After reset
INT3 interrupt control register UART1 BUS collision detection interrupt control register UART0 BUS collision detection interrupt control register SI/O4 interrupt control register (S4IC) SI/O3 interrupt control register UART2 Bus collision detection interrupt control register DMA0 interrupt control register DMA1 interrupt control register
INT3IC U1BCNIC U0BCNIC S4IC S3IC BCNIC DM0IC DM1IC
XX00?0002 XXXX?0002 XXXX?0002 XX00?0002 XX00?0002 XXXX?0002 XXXX?0002 XXXX?0002
UART2 transmit interrupt control register UART2 receive interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register
Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register
S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC
XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002
INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register
INT0IC INT1IC INT2IC
XX00?0002 XX00?0002 XX00?0002
Note :The blank areas are reserved and cannot be used by users. X : Nothing is mapped to this bit ? : Undefined
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M16C/6S Group
SFR
Address 008016 008116 008216 008316 008416 008516 008616
Register
Symbol
After reset
~
01B016 01B116 01B216 01B316 01B416 01B516 01B616 01B716 01B816 01B916 01BA16 01BB16 01BC16 01BD16 01BE16 01BF16
~
Flash memory control register 1 Flash memory control register 0 Address match interrupt register 2
(Note 2) (Note 2)
FMR1 FMR0 RMAD2
0?00??0?2 ??0000012 0016 0016 X016 XXXXXX002 0016 0016 X016
Address match interrupt enable register 2
Address match interrupt register 3
AIER2 RMAD3
~
025016 025116 025216 025316 025416 025516 025616 025716 025816 025916 025A16 025B16 025C16 025D16 025E16 025F16
~
Peripheral clock select register
PCLKR
000000112
~
033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16
~
Note 1: The blank areas are reserved and cannot be used by users. Note 2: This register is included in the flash memory version. X : Nothing is mapped to this bit ? : Undefined
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M16C/6S Group
SFR
Address 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16
Register
Symbol
After reset
Interrupt cause select register 2 Interrupt cause select register SI/O3 transmit/receive register SI/O3 control register SI/O3 bit rate generator SI/O4 transmit/receive register SI/O4 control register SI/O4 bit rate generator
IFSR2A IFSR S3TRR S3C S3BRG S4TRR S4C S4BRG
00XXXXXX2 0016 ??16 010000002 ??16 ??16 010000002 ??16
UART0 special mode register 4 UART0 special mode register 3 UART0 special mode register 2 UART0 special mode register UART1 special mode register 4 UART1 special mode register 3 UART1 special mode register 2 UART1 special mode register UART2 special mode register 4 UART2 special mode register 3 UART2 special mode register 2 UART2 special mode register
UART2 transmit/receive mode register UART2 bit rate generator UART2 transmit buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register
U0SMR4 U0SMR3 U0SMR2 U0SMR U1SMR4 U1SMR3 U1SMR2 U1SMR U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB
0016 000X0X0X2 X00000002 X00000002 0016 000X0X0X2 X00000002 X00000002 0016 000X0X0X2 X00000002 X00000002 0016 ??16 ????????2 XXXXXXX?2 000010002 000000102 ????????2 ?????XX?2
Note : The blank areas are reserved and cannot be used by users. X : Nothing is mapped to this bit ? : Undefined
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M16C/6S Group
SFR
Address 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16
Register Count start flag One-shot start flag Trigger select register Up-down flag Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register
Symbol TABSR ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4
After reset 0016 0016 0016 0016 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16
Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register
TA0MR TA1MR TA2MR TA3MR TA4MR
0016 0016 0016 0016 0016
UART0 transmit/receive mode register
UART0 bit rate generator UART0 transmit buffer register
UART0 transmit/receive control register 0 UART0 transmit/receive control register 1
U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON
UART0 receive buffer register
UART1 transmit/receive mode register
UART1 bit rate generator UART1 transmit buffer register
UART1 transmit/receive control register 0 UART1 transmit/receive control register 1
UART1 receive buffer register
UART transmit/receive control register 2
0016 ??16 ????????2 XXXXXXX?2 000010002 000000102 ????????2 ?????XX?2 0016 ??16 ????????2 XXXXXXX?2 000010002 000000102 ????????2 ?????XX?2 X00000002
DMA0 request cause select register DMA1 request cause select register
DM0SL DM1SL
0016 0016
Note : The blank areas are reserved and cannot be used by users. X : Nothing is mapped to this bit ? : Undefined
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M16C/6S Group
SFR
Address
03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16
Register
Symbol
After reset
Port P1 register Port P1 direction register
P1 PD1
??16 0016
Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P9 register Port P8 direction register Port P9 direction register
P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9
??16 ??16 0016 0016 ??16 ??16 0016 0016 ??16 ??16 00X000002 0016
Pull-up control register 0 Pull-up control register 1 Pull-up control register 2 Port control register
PUR0 PUR1 PUR2 PCR
0016
000000002
0016 0016
Note 1: The blank areas are reserved and cannot be used by users. X : Nothing is mapped to this bit ? : Undefined
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M16C/6S Group
Reset
Reset
There are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscillation stop detection reset.
Hardware Reset
____________ ____________
A reset is applied using the RESET pin. When an "L" signal is applied to the RESET pin while the power supply voltage is within the recommended operating condition, the pins are initialized (see Table 1.5.1). The oscillation circuit is initialized and the main clock starts oscillating. When the input ____________ level at the RESET pin is released from "L" to "H", the CPU and SFR are initialized, and the program is executed starting from the address indicated by the reset vector. The internal RAM is not initialized. ____________ If the RESET pin is pulled "L" while writing to the internal RAM, the internal RAM becomes indeterminate. Figure 1.5.1 shows the example reset circuit. Figure 1.5.2 shows the reset sequence. Table 1.5.1 ____________ shows the statuses of the other pins while the RESET pin is "L". Figure 1.5.3 shows the CPU register status after reset. Refer to "SFR" for SFR status after reset. 1. When the power supply is stable
____________
(1) Apply an "L" signal to the RESET pin. (2) Supply a clock for 20 cycles or more to the XIN pin. ____________ (3) Apply an "H" signal to the RESET pin. 2. Power on ____________ (1) Apply an "L" signal to the RESET pin. (2) Let the power supply voltage increase until it meets the recommended operating condition. (3) Wait td(P-R) or more until the internal power supply stabilizes. (4) Supply a clock for 20 cycles or more to the XIN pin. ____________ (5) Apply an "H" signal to the RESET pin.
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M16C/6S Group
Reset
Software Reset
When the PM03 bit in the PM0 register is set to "1" (microcomputer reset), the microcomputer has its pins, CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset vector. Select the main clock for the CPU clock source, and set the PM03 bit to "1" with main clock oscillation satisfactorily stable. At software reset, some SFR's are not initialized. Refer to "SFR". Also, since the PM01 to PM00 bits in the PM0 register are not initialized, the processor mode remains unchanged.
VCC 0V RESET VCC RESET 0V
Recommended operating voltage
Equal to or less than 0.2VCC
Equal to or less than 0.2VCC More than 20 cycles of XIN + td(P-R) are needed.
Figure 1.5.1. Example Reset Circuit
Watchdog Timer Reset
Where the PM12 bit in the PM1 register is "1" (reset when watchdog timer underflows), the microcomputer initializes its pins, CPU and SFR if the watchdog timer underflows. Then the program is executed starting from the address indicated by the reset vector. At watchdog timer reset, some SFR's are not initialized. Refer to "SFR". Also, since the PM01 to PM00 bits in the PM0 register are not initialized, the processor mode remains unchanged.
Oscillation Stop Detection Reset
Where the CM27 bit in the CM2 register is "0" (reset at oscillation stop detection), the microcomputer initializes its pins, CPU and SFR, coming to a halt if it detects main clock oscillation circuit stop. Refer to the section "oscillation stop, re-oscillation detection function". At oscillation stop detection reset, some SFR's are not initialized. Refer to the section "SFR". Also, since the PM01 to PM00 bits in the PM0 register are not initialized, the processor mode remains unchanged.
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M16C/6S Group
Reset
VCC1 XIN td(P-R) More than 20 cycles are needed
RESET
BCLK
28cycles
BCLK
Single chip mode Internal address
FFFFC16 FFFFE16
Content of reset vector
Figure 1.5.2. Reset Sequence
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M16C/6S Group
Reset
____________
Table 1.5.1. Pin Status When RESET Pin Level is "L"
Status Pin name
P15, P60 to P67, P70, P71, P73, P74, P76, P80, P81, P83, P84, P85, P90 to P92, TS CNVSS = VSS Input port
b15
b0
000016 000016 000016 000016 000016 000016 000016
Data register(R0) Data register(R1) Data register(R2) Data register(R3) Address register(A0) Address register(A1) Frame base register(FB)
b0
b19
0000016 Content of addresses FFFFE16 to FFFFC16
b15 b0
Interrupt table register(INTB) Program counter(PC)
000016 000016 000016
b15 b0
User stack pointer(USP) Interrupt stack pointer(ISP) Static base register(SB)
000016
b15 b8 b7 b0
Flag register(FLG)
IPL
UI
OBS Z DC
Figure 1.5.3. CPU Register Status After Reset
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M16C/6S Group
Processor Mode
Processor Mode
(1) Setting Processor Modes
Processor mode is available only: single-chip mode. Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register. Table 1.6.2 shows the processor mode after hardware reset. Table 1.6.3 shows the PM01 to PM00 bit set values and processor modes. For setting Single-chip mode. CNVss should be kept Vss level. And PM01 to PM00 of PM0 register should be set "00." Table 1.6.1. Processor Mode After Hardware Reset
CNVSS pin input level VSS VCC
Processor mode Single-chip mode Flash Memory Mode
Table 1.6.2. PM01 to PM00 Bits Set Values and Processor Modes
PM01 to PM00 bits 002 012 102 112 Must not be set Processor modes Single-chip mode
Figure 1.6.4 show the memory map in single chip mode.
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M16C/6S Group
Processor Mode
(3) Setting PLC Mode
PLC mode is simply set by putting P15 High level during RESET.
TR
RESET
P15
Tsetup THOLD
Figure 1.6.1. PLC mode by P15 simply setting
Table 1.6.3.
min TR Tset up THOLD 40us 5us 5us
typ
max
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M16C/6S Group
Processor Mode
Processor mode register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PM0
Address 000416
After reset (Note 2) 000000002 (CNVSS pin = "L") 000000112 (CNVSS pin = "H")
Bit symbol
PM00 PM01
Bit name
Processor mode bit (Note 2)
b1 b0
Function
0 0: Single-chip mode 0 1: Must not be set 1 0: Must not be set 1 1: Must not be set
RW RW RW
(b2) PM03
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Software reset bit
Setting this bit to "1" resets the microcomputer. When read, its content is "0".
RW
(b7-b4)
Nothing is assigned. When write, set to "0". When read, their contents are indeterminate.
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable). Note 2: The PM01 to PM00 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.
Figure 1.6.2. PM0 Register
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
1
0
Symbol PM1
Address 000516
After reset 0X0010002
Bit symbol
(b0)
(b2)
Bit name
Reserved bit
Function
Should be set to "0".
RW RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
PM12 PM13
Watchdog timer function select bit Internal reserved area expansion bit
0 : Watchdog timer interrupt 1 : Watchdog timer reset (Note 2) Should be set to "1".
RW RW
(b5-b4)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b6) PM17
Reserved bit Wait bit (Note 3)
Should be set to "0". 0 : No wait state 1 : With wait state (1 wait)
RW RW
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable). Note 2: PM12 bit is set to "1" by writing a "1" in a program. (Writing a "0" has no effect.) Note 3: When PM17 bit is set to "1" (with wait state), one wait state is inserted when accessing the internal RAM, internal ROM, or an external area.
Figure 1.6.3. PM1 Register Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 25 of 190
M16C/6S Group
Processor Mode
Single-chip mode
0000016 0040016 Internal RAM XXXXX16 PM13=1 (Note1) Internal RAM Capacity Address XXXXX16 Can not use 24K bytes 063FF16 SFR
Internal ROM Capacity Address YYYYY16 96K bytes E800016
YYYYY16 Internal ROM FFFFF16 Note 1: Since internal RAM which can be used becomes 15 K bytes when PM13 is 0 , please be sure to set PM13 to 1.
Figure 1.6.4. Memory Map in Single Chip Mode
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M16C/6S Group
Clock Generation Circuit
Clock Generation Circuit
The clock generation circuit contains two oscillator circuits as follows: (1) Main clock oscillation circuit (2) On-chip Oscillator (oscillation stop detect function) Table 1.7.1 lists the clock generation circuit specifications. Figure 1.7.1 shows the clock generation circuit. Figures 1.7.2 to 1.7.6 show the clock-related registers. Table 1.7.1. Clock Generation Circuit Specifications
Item Use of clock Main clock oscillation circuit * CPU clock source * Peripheral function clock source 5.12 MHz * Crystal oscillator (Note 1) XIN, XOUT On-chip Oscillator * CPU clock source * Peripheral function clock source
Clock frequency Usable oscillator Pins to connect oscillator Oscillation stop, restart function Oscillator status after reset Other
About 1 MHz
No Oscillating Externally derived clock can be input
Presence Stopped
Note. Operating frequency must be 5.12 MHz, overall accuracy must be less than 150 ppm.
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M16C/6S Group
Clock Generation Circuit
f1 PCLK0=1 f2 XIN XOUT
CM21 5.12MHz
PCLK0=0 f8
On-chip oscillator
On-chip oscillator clock
f32 fAD
46.08MHz
15.36MHz
PLL
1/3
IT800 CLK_IN
Oscillation stop, reoscillation detection circuit
f1SIO PCLK1=1 f2SIO PCLK1=0 f8SIO f32SIO
CM10=1(stop mode)
SQ R
CM21=1
ebc a
Main clock
CM21=0
Divider
d
CM07=0 CPU clock BCLK
CM02 S WAIT instruction R Q
e a
RESET Software reset
b
1/2 1/2 1/4 1/8 1/2 1/16 1/2
c
1/32
1/2 1/2
CM06=0 CM17-CM16=112 CM06=1 CM06=0 CM17-CM16=102
Interrupt request level judgment output
d
CM02, CM04, CM05, CM06, CM07: CM0 register bits CM10, CM11, CM16, CM17: CM1 register bits PCLK0, PCLK1: PCLK register bits CM21, CM27 : CM2 register bits
CM06=0 CM17-CM16=012 CM06=0 CM17-CM16=002
Details of divider
Oscillation stop, re-oscillation detection circuit(Note)
Main clock
Pulse generation circuit for clock edge detection and charge, discharge control
CM27
Charge, discharge circuit
0 1
Reset generating circuit
Oscillation stop detection reset Oscillation stop, re-oscillation detection signal
Oscillation stop, re-oscillation detection interrupt generating circuit
CM21 switch signal
Note. Even if Xin input stops, PLL does not stop. Oscillation stop, re-oscillation detect circuit does not function.
Figure 1.7.1. Clock Generation Circuit
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M16C/6S Group
Clock Generation Circuit
System clock control register 0 (Notes 1 and 4)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol CM0 Bit symbol
(b1-b0)
Address 000616 Bit name
After reset 010010002 Function RW
Nothing is assigned. When write, set to "0". When read, its content is indeterminate. WAIT peripheral function clock stop bit (Note 3) 0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode
CM02
RW
(b4-b3) (b5)
Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Reserved bit Main clock division select bit 0 (Notes 5, 13) Reserved bit Should be set to "0". 0 : CM16 and CM17 valid 1 : Division by 8 mode Should be set to "0".
RW RW RW
CM06
(b7)
Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable). Note 2: When entering stop mode from high or middle speed mode, On-chip Oscillator mode or On-chip Oscillator low power mode, the CM06 bit is set to "1" (divide-by-8 mode). Note 3: When the PM21 bit of PM2 register is set to "1" (clock modification disable), writing to the CM02 bits has no effect. Note 4: To use the main clock as the clock source for the CPU clock, follow the procedure below. (1) Wait until td(M-L) elapses or the main clock oscillation stabilizes, whichever is longer. (2) Set the CM21 to "0". Note 5: During On-chip Oscillator low power dissipation mode, the divide-by-n value can be selected using the CM06 and CM17 to CM16 bits. To return to high or middle speed mode, however, set the CM06 bit to "1", before selecting the desired mode.
Figure 1.7.2. CM0 Register
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M16C/6S Group
Clock Generation Circuit
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
1
00
00
Symbol CM1 Bit symbol
CM10
Address 000716 Bit name All clock stop control bit (Notes 3, 4)
Reserved bit Reserved bit Main clock division select bit 1 (Note 2)
After reset 001000002 Function
0 : Clock on 1 : All clocks off (stop mode) Must set to "0" Must set to "1"
b7 b6
RW RW RW RW RW RW
(b4-b1) (b5) CM16 CM17
0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode
Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable). Note 2: Effective when the CM06 bit is "0" (CM16 and CM17 bits enable). Note 3: When the CM20 bit of CM2 register is set to "1" (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to "1". Note 4: When the PM21 bit of PM2 register is set to "1" (clock modification disable), writing to the CM10 bits has no effect. When the PM22 bit of PM2 register is set to "1" (watchdog timer count source is On-chip Oscillator clock), writing to the CM10 bit has no effect.
Figure 1.7.3. CM1 Register
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M16C/6S Group
Clock Generation Circuit
Oscillation stop detection register (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
00
Symbol CM2 Bit symbol
CM20
Address 000C16 Bit name
Oscillation stop, reoscillation detection bit (Notes 7, 8, 9, 10) System clock select bit 2 (Notes 2, 3, 6, 10)
After reset 0X0000002(Note 10) Function
0: Oscillation stop, re-oscillation detection function disabled 1: Oscillation stop, re-oscillation detection function enabled 0: Main clock (On-chip Oscillator turned off) 1: On-chip Oscillator clock (On-chip Oscillator oscillating) 0: Main clock stop, re-oscillation not detected 1: Main clock stop, re-oscillation detected 0: Main clock oscillating 1: Main clock turned off Must set to "0"
RW RW
CM21
RW
CM22
Oscillation stop, reoscillation detection flag (Note 4) XIN monitor flag (Note 5) Reserved bit
RW
CM23 (b5-b4) (b6) CM27
RO RW
Nothing is assigned. When write, set to "0". When read, its content is indeterminate.
0: Oscillation stop detection reset Operation select bit (when an oscillation stop, 1: Oscillation stop, re-oscillation RW detection interrupt re-oscillation is detected) (Note 10) Note 1: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable). Note 2: When the CM20 bit is "1" (oscillation stop, re-oscillation detection function enabled), the CM27 bit is "1" (oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the CM21 bit is set to "1" (On-chip Oscillator clock) if the main clock stop is detected. Note 3: If the CM20 bit is "1" and the CM23 bit is "1" (main clock turned off), do not set the CM21 bit to "0". Note 4: This bit becomes "1" at main clock stop detection and main clock re-oscillation detection. When this bit changes from "0" to "1", there arise oscillation stop, re-oscillation detection interrupt. Use this register to discriminate the causes for oscillation stop, re-oscillation detection interrupt and watchdog timer interrupt in the interrupt processing program. By writing "0" in the program, this bit becomes "0". (Even when "1" is written in the program, no change is identified for the bit. Also, this bit is not set to "0" where there occur oscillation stop, re-oscillation detection interrupt.) When the CM22 bit is "1", no oscillation stop, reoscillation detection interrupt occur even if oscillation stop or re-oscillation is detected. Note 5: Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine the main clock status. Note 6: Effective when the CM07 bit of CM0 register is "0". Note 7: When the PM21 bit of PM2 register is "1" (clock modification disabled), writing to the CM20 bit has no effect. Note 8: Set the CM20 bit to "0" (disable) before entering stop mode. After exiting stop mode, set the CM20 bit back to "1" (enable). Note 9: Set the CM20 bit to "0" (disable) before setting the CM05 bit of CM0 register. Note 10: The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.
Figure 1.7.4. CM2 Register
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M16C/6S Group
Clock Generation Circuit
Peripheral clock select register (Note)
b7 b6 b5 b4 b3 b2 b1 b0
000000
Symbol PCLKR
Address 025E16
When reset 000000112
Bit symbol PCLK0
Bit name
Timers A, B clock select bit (Clock source for the timers A, B, and the dead time timer) SI/O clock select bit (Clock source for UART0 to UART2, SI/O3, SI/O4) 0 : f2 1 : f1
Function
RW RW
PCLK1
0 : f2SIO 1 : f1SIO Must set to "0"
RW
(b7-b2)
Reserved bit
RW
Note: Write to this register after setting the PRC0 bit of PRCR register to "1" (write enable).
Processor mode register 2 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol PM2 Address 001E16 After reset XXX000002
Bit symbol (b0) PM21
Bit name
Function
RW
Nothing is assigned. When write, set to "0". When read, its content is interdeterminate. System clock protective bit (Note 2, Note 3) WDT count source protective bit (Note 2, Note 4) 0 : Clock is protected by PRCR register 1 : Clock modification disabled
RW
PM22
0 : CPU clock is used for the watchdog timer count source RW 1 : On-chip Oscillator clock is used for the watchdog timer count source Must set to "0" RW
Reserved bit (b4-b3) (b7-b5)
Nothing is assigned. When write, set to "0". When read, its content is interdeterminate.
Note 1: Write to this register after setting the PRC1 bit of PRCR register to "1" (write enable). Note 2: Once this bit is set to "1", it cannot be cleared to "0" in a program. Note 3: Setting the PM21 bit to "1" results in the following conditions: * The BCLK is not halted by executing the WAIT instruction. * Writing to the following bits has no effect. CM02 bit of CM0 register CM05 bit of CM0 register (main clock is not halted) CM07 bit of CM0 register CM10 bit of CM1 register (stop mode is not entered) CM11 bit of CM1 register CM20 bit of CM2 register (oscillation stop, re-oscillation detection function settings do not change) Note 4: Setting the PM22 bit to "1" results in the following conditions: * The On-chip Oscillator starts oscillating, and the On-chip Oscillator clock becomes the watchdog timer count source. * The CM10 bit of CM1 register is disabled against write. (Writing a "1" has no effect, nor is stop mode entered.) * The watchdog timer does not stop when in wait mode or hold state.
Figure 1.7.5. PCLKR Register and PM2 Register
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Clock Generation Circuit
The following describes the clocks generated by the clock generation circuit.
(1) Main Clock
Main clock is supplied by IT800 with a tripled clock of XIN (main clock oscillator). This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a feedback resistor. The main clock oscillator circuit may also be configured by feeding an externally generated clock to the XIN pin. Figure 1.7.6 shows the examples of main clock connection circuit. After reset, the main clock divided by 8 is selected for the CPU clock. Even if Xin input stops, main clock ocsillator does not stop. During stop mode, all clocks of internal M16C core including the main clock are turned off. Refer to "power control".
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
XIN
XOUT (Note 1) Rd
XIN
XOUT Open
(Note 2)
Externally derived clock COUT Vcc Vss
CIN
Note 1: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN and XOUT following the instruction. Note 2: Operating frequency must be 5.12 MHz, overall accuracy must be less than 150 ppm.
Figure 1.7.6. Examples of Main Clock Connection Circuit
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Clock Generation Circuit
(3) On-chip Oscillator Clock
This clock, approximately 1 MHz, is supplied by a On-chip Oscillator. This clock is used as the clock source for the CPU and peripheral function clocks. In addition, if the PM22 bit of PM2 register is "1" (Onchip Oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer. After reset, the On-chip Oscillator clock is turned off. It is turned on by setting the CM21 bit of CM2 register to "1" (On-chip Oscillator clock), and is used as the clock source for the CPU and peripheral function clocks, in place of the main clock.
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Clock Generation Circuit
CPU Clock and Peripheral Function Clock
Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral functions.
(1) CPU Clock and BCLK
These are operating clocks for the CPU and watchdog timer. The clock source for the CPU clock can be chosen to be the main clock, or On-chip Oscillator clock. If the main clock or On-chip Oscillator clock is selected as the clock source for the CPU clock, the selected clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in CM0 register and the CM17 to CM16 bits in CM1 register to select the divide-by-n value. After reset, the main clock divided by 8 provides the CPU clock. Note that when entering stop mode from high or middle speed mode or On-chip Oscillator mode, the CM06 bit of CM0 register is set to "1" (divide-by-8 mode).
(2) Peripheral Function Clock(f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO)
These are operating clocks for the peripheral functions. Of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, or On-chip Oscillator clock by dividing them by i. The clock fi is used for timers A, and fiSIO is used for serial I/O. When the WAIT instruction is executed after setting the CM02 bit of CM0 register to "1" (peripheral function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode, the fi, and fiSIO clocks are turned off.
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Clock Generation Circuit
Power Control
There are three power control modes. For convenience' sake, all modes other than wait and stop modes are referred to as normal operation mode here.
(1) Normal Operation Mode
Normal operation mode is further classified into three modes. In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are turned off, the power consumption is further reduced. Before the clock sources for the CPU clock can be switched over, the new clock source to which switched must be oscillating stably. If the new clock source is the main clock, allow a sufficient wait time in a program until it becomes oscillating stably. Where the CPU clock source is changed from the On-chip Oscillator to the main clock, change the operation mode to the medium speed mode (divided by 8 mode) after the clock was divided by 8 (the CM06 bit of CM0 register was set to "1") in the On-chip Oscillator mode. * High-speed Mode The main clock divided by 1 provides the CPU clock. * Medium-speed Mode The main clock divided by 2, 4, 8 or 16 provides the CPU clock. * On-chip Oscillator Mode The On-chip Oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The Onchip Oscillator clock is also the clock source for the peripheral function clocks.
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Clock Generation Circuit
Table 1.7.2. Setting Clock Related Bit and Modes
Modes High-speed mode Mediumdivided by 2 speed divided by 4 mode divided by 8 divided by 16 On-chip divided by 1 oscillator divided by 2 mode divided by 4 divided by 8 divided by 16 CM2 register CM21 0 0 0 0 0 1 1 1 1 1 CM1 register CM17, CM16 002 012 102 112 002 012 102 112 CM0 register CM06 0 0 0 1 0 0 0 0 1 0
Note: The divide-by-n value can be selected the same way as in On-chip Oscillator mode.
(2) Wait Mode
In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the watchdog timer. However, if the PM22 bit of PM2 register is "1" (On-chip Oscillator clock for the watchdog timer count source), the watchdog timer remains active. Because the main clock, and On-chip Oscillator clock are on, the peripheral functions using these clocks keep operating. * Peripheral Function Clock Stop Function If the CM02 bit is "1" (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO, f8SIO, and f32SIO clocks are turned off when in wait mode, with the power consumption reduced that much. * Entering Wait Mode The microcomputer is placed into wait mode by executing the WAIT instruction. * Pin Status During Wait Mode Table 1.7.3 lists pin status during wait mode * Exiting Wait Mode The microcomputer is moved out of wait mode by a hardware reset or peripheral function interrupt. If the microcomputer is to be moved out of exit wait mode by a hardware reset, set the peripheral function interrupt priority ILVL2 to ILVL0 bits to "0002" (interrupts disabled) before executing the WAIT instruction. The peripheral function interrupts are affected by the CM02 bit. If CM02 bit is "0" (peripheral function clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait mode. If CM02 bit is "1" (peripheral function clocks turned off during wait mode), the peripheral functions using the peripheral function clocks stop operating, so that only the peripheral functions clocked by external signals can be used to exit wait mode. Table 1.7.4 lists the interrupts to exit wait mode.
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Clock Generation Circuit
Table 1.7.3. Pin Status During Wait Mode Pin I/O ports Status Retains status before wait mode
Table 1.7.4. Interrupts to Exit Wait Mode
Interrupt Serial I/O interrupt Timer A interrupt INT interrupt CM02=0 Can be used when operating with internal or external clock Can be used in all modes Can be used CM02=1 Can be used when operating with external clock Can be used in event counter mode Can be used
If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the following before executing the WAIT instruction. 1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the periph eral function interrupt to be used to exit wait mode. Also, for all of the peripheral function interrupts not used to exit wait mode, set the ILVL2 to ILVL0 bits to "0002" (interrupt disable). 2. Set the I flag to "1". 3. Enable the peripheral function whose interrupt is to be used to exit wait mode. In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an interrupt routine is executed. The CPU clock turned on when exiting wait mode by a peripheral function interrupt is the same CPU clock that was on when the WAIT instruction was executed.
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Clock Generation Circuit
(3) Stop Mode
In stop mode, all the M16C core's internal oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. However, the peripheral functions clocked by external signals keep operating. The following interrupts can be used to exit stop mode. ______ * INT interrupt * Timer A, interrupt (when counting external pulses in event counter mode) * Serial I/O interrupt (when external clock is selected) * Entering Stop Mode The microcomputer is placed into stop mode by setting the CM10 bit of CM1 register to "1" (all clocks turned off). At the same time, the CM06 bit of CM0 register is set to "1" (divide-by-8 mode). Before entering stop mode, set the CM20 bit to "0" (oscillation stop, re-oscillation detection function disable). * Pin Status in Stop Mode Table 1.9.6 lists pin status during stop mode * Exiting Stop Mode The microcomputer is moved out of stop mode by a hardware reset or peripheral function interrupt. If the microcomputer is to be moved out of stop mode by a hardware reset, set the peripheral function interrupt priority ILVL2 to ILVL0 bits to "0002" (interrupts disable) before setting the CM10 bit to "1". If the microcomputer is to be moved out of stop mode by a peripheral function interrupt, set up the following before setting the CM10 bit to "1". 1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the peripheral function interrupt to be used to exit stop mode. Also, for all of the peripheral function interrupts not used to exit stop mode, set the ILVL2 to ILVL0 bits to "0002". 2. Set the I flag to "1". 3. Enable the peripheral function whose interrupt is to be used to exit stop mode. In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an interrupt service routine is executed. Which CPU clock will be used after exiting stop mode by a peripheral function is determined by the CPU clock that was on when the microcomputer was placed into stop mode as follows: If the CPU clock before entering stop mode was derived from the main clock: main clock divide-by-8 If the CPU clock before entering stop mode was derived from the On-chip Oscillator clock: On-chip Oscillator clock divide-by-8
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Clock Generation Circuit
Table 1.7.5. Pin Status in Stop Mode Pin I/O ports Status Retains status before stop mode
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Clock Generation Circuit
Figure 1.7.7 shows the state transition from normal operation mode to stop mode and wait mode. Figure 1.7.8 shows the state transition in normal operation mode. Table 1.7.6 shows a state transition matrix describing allowed transition and setting. The vertical line shows current state and horizontal line shows state after transition.
Reset
All oscillators stopped
WAIT instruction (Note 1) Interrupt WAIT instruction (Note 1)
CM10=1
CPU operation stopped
Stop mode
Interrupt Interrupt
Medium-speed mode (divided-by-8 mode)
Wait mode
Stop mode
CM10=1
High-speed, mediumspeed mode
Wait mode
Interrupt
CM10=1
Stop mode
Interrupt (Note 2)
On-chip Oscillator mode
WAIT instruction (Note 1) Interrupt
Wait mode
Normal mode
Note 1: When the PM21 bit = 0 (system clock protective function unused). Note 2: The On-chip Oscillator clock divided by 8 provides the CPU clock. Note 3: Write to the CM0 register and CM1 register simultaneously by accessing in word units while CM21=0 (On-chip Oscillator turned off).
Figure 1.7.7. State Transition to Stop Mode and Wait Mode
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Clock Generation Circuit
Main clock oscillation
On-chip Oscillator clock oscillation
High-speed mode
CPU clock: f(XIN)
Middle-speed mode (divide by 2)
CPU clock: f(XIN)/2
Middle-speed mode (divide by 4)
CPU clock: f(XIN)/4
Middle-speed mode Middle-speed mode (divide by 8) (divide by 16)
CPU clock: f(XIN)/8 CPU clock: f(XIN)/16
On-chip Oscillator mode CM21=0 (Note 4) CPU clock f(Ring) f(Ring)/2 f(Ring)/4 f(Ring)/8 f(Ring)/16
CM07=0 CM06=0 CM17=0 CM16=0
CM07=0 CM06=0 CM17=0 CM16=1
CM07=0 CM06=0 CM17=1 CM16=0
CM07=0 CM06=1
CM07=0 CM06=0 CM17=1 CM16=1 (Note 2) CM21=1
(Note 3)
Notes: 1: Avoid making a transition when the CM20 bit is set to "1" (oscillation stop, re-oscillation detection function enabled). Set the CM20 bit to "0" (oscillation stop, re-oscillation detection function disabled) before transiting. 2: Set the CM06 bit to "1" (division by 8 mode) before changing back the operation mode from On-chip Oscillator mode to high- or middle-speed mode. 3: Please change according to the direction of an arrow. 4: When you return to high-speed and middle-speed mode from On-chip Oscillator mode, please make CM06 into "1" (divide by 8) mode.
Figure 1.7.8. State Transition in Normal Mode
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Clock Generation Circuit
Table 1.7.6. Allowed Transition and Setting
State after transition
High-speed mode, On-chip Oscillator middle-speed mode mode High-speed mode, middle-speed mode Stop mode Wait mode
See Table A (6)2 (10)3 (10)
(7) See Table A (10)3 (10)
(8)1 (8)1
(9) (9) --
Current state
On-chip Oscillator mode
Stop mode
Wait mode
---: Cannot transit
Table 1. State Transition with Main Clock Division Ration in High- or Middle-speed Mode and On-chip Oscillator Mode.
Table B. Setting and Operation Setting Operation CPU clock no division mode CPU clock division by 2 mode CPU clock division by 4 mode CPU clock division by 16 mode CPU clock division by 8 mode Main clock On-chip Oscillator clock selected Transition to stop mode Transition to wait mode Exit stop mode or wait mode
State after transition No division No division
Divided by 2 Divided by 4 Divided by 8 Divided by 16
Divided by 2
Divided by 4
Divided Divided by 8 by 16
(1) (2) (3) (4) (5) (6) (7) (8) (9) (10)
(2) (1) (1) (1) (1) (2) (2) (2)
(3) (3) (3) (3)
(5) (5) (5) (5)
(4) (4) (4) (4)
CM06 = 0, CM17 = 0 , CM16 = 0 CM06 = 0, CM17 = 0 , CM16 = 1 CM06 = 0, CM17 = 1 , CM16 = 0 CM06 = 0, CM17 = 1 , CM16 = 1 CM06 = 1 CM21 = 0 CM21 = 1 CM10 = 1 wait Hardware interrupt
Notes: 1. Avoid making a transition when the CM21 bit is set to "1" (oscillation stop, re-oscillation detection function enabled). Set the CM21 bit to "0" (oscillation stop, re-oscillation detection function disabled) before transiting. 2. Set the CM06 bit to "1" (division by 8 mode) before transiting from On-chip Oscillator mode to high- or middle-speed mode. 3. When exiting stop mode, the CM06 bit is set to "1" (division by 8 mode).
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Current state
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M16C/6S Group
Clock Generation Circuit
System Clock Protective Function
When the main clock is selected for the CPU clock source, this function disables the clock against modifications in order to prevent the CPU clock from becoming halted by run-away. If the PM21 bit of PM2 register is set to "1" (clock modification disabled), the following bits are protected against writes: * CM02 bit in CM0 register * CM10, CM11 bits in CM1 register * CM20 bit in CM2 register Before the system clock protective function can be used, the following register settings must be made: (1) Set the PRC1 bit of PRCR register to "1" (enable writes to PM2 register). (2) Set the PM21 bit of PM2 register to "1" (disable clock modification). (3) Set the PRC1 bit of PRCR register to "0" (disable writes to PM2 register). Do not execute the WAIT instruction when the PM21 bit is "1".
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M16C/6S Group
Clock Generation Circuit
Oscillation Stop and Re-oscillation Detect Function
The oscillation stop and re-oscillation detect function is such that main clock oscillation circuit stop and reoscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, re-oscillation detection interrupt are generated. Which is to be generated can be selected using the CM27 bit of CM2 register. Main clock oscillator of M16C/6S does not stop even if Xin input stops. Oscillation stop re-oscillation detect circuit does not function.
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M16C/6S Group
Protection
Protection
In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 1.8.1 shows the PRCR register. The following lists the registers protected by the PRCR register. * Registers protected by PRC0 bit: CM0, CM1, CM2, and PCLKR registers * Registers protected by PRC1 bit: PM0, PM1, PM2 registers * Registers protected by PRC2 bit: PD9, S3C and S4C registers Set the PRC2 bit to "1" (write enabled) and then write to any address, and the PRC2 bit will be cleared to "0" (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to "1". Make sure no interrupts or DMA transfers will occur between the instruction in which the PRC2 bit is set to "1" and the next instruction. The PRC0 and PRC1 bits are not automatically cleared to "0" by writing to any address. They can only be cleared in a program.
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol PRCR Bit symbol
PRC0
Address 000A16 Bit name
Protect bit 0
After reset XX0000002 Function
Enable write to CM0, CM1, CM2, PLC0 and PCLKR registers 0 : Write protected 1 : Write enabled Enable write to PM0, PM1, PM2, TB2SC, INVC0 and INVC1 registers 0 : Write protected 1 : Write enabled
RW
RW
PRC1
Protect bit 1
RW
PRC2
Protect bit 2
Enable write to PD9, S3C and S4C registers 0 : Write protected 1 : Write enabled
RW
(b5-b3)
Reserved bit
Must set to "0"
RW
(b7-b6)
Nothing is assigned. When write, set to "0". When read, its content is interdeterminate.
Note: The PRC2 bit is set to "0" by writing to any address after setting it to "1". Other bits are not set to "0" by writing to any address, and must therefore be set in a program.
Figure 1.8.1. PRCR Register
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M16C/6S Group
Interrupts
Interrupts
Type of Interrupts
Figure 1.9.1 shows types of interrupts.
Software (Non-maskable interrupt)
Hardware
Special (Non-maskable interrupt)
Peripheral function (Note 1) (Maskable interrupt)
Note 1: Peripheral function interrupts are generated by the microcomputer's internal functions. Note 2: Do not normally use this interrupt because it is provided exclusively for use by development support tools. Figure 1.9.1. Interrupts
* Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. * Non-maskable I0nterrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level.
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Interrupt

Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction
________

DBC (Note 2) Watchdog timer Single step (Note 2) Address match
M16C/6S Group
Interrupts
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. * Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. * Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag set to "1" (the operation resulted in an overflow). The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB * BRK Interrupt A BRK interrupt occurs when executing the BRK instruction. * INT Instruction Interrupt An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63 can be specified for the INT instruction. Because software interrupt Nos. 4 to 31 are assigned to peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the INT instruction. In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is cleared to "0" (ISP selected) before executing an interrupt sequence. The U flag is restored from the stack when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not change state during instruction execution, and the SP then selected is used.
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Interrupts
Hardware Interrupts
Hardware interrupts are classified into two types -- special interrupts and peripheral function interrupts. (1) Special Interrupts Special interrupts are non-maskable interrupts. ________ * DBC Interrupt Do not normally use this interrupt because it is provided exclusively for use by development support tools. * Watchdog Timer Interrupt Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize the watchdog timer. For details about the watchdog timer, refer to the section "watchdog timer". * Oscillation Stop and Re-oscillation Detection Interrupt Generated by the oscillation stop and re-oscillation detection function. For details about the oscillation stop detection function, refer to the section "clock generating circuit". * Single-step Interrupt Do not normally use this interrupt because it is provided exclusively for use by development support tools. * Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMAD0 to RMAD3 register that corresponds to one of the AIER register's AIER0 or AIER1 bit or the AIER2 register's AIER20 or AIER21 bit which is "1" (address match interrupt enabled). For details about the address match interrupt, refer to the section "address match interrupt". (2) Peripheral Function Interrupts Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal functions. The interrupt sources for peripheral function interrupts are listed in Table 1.9.2. For details about the peripheral functions, refer to the description of each peripheral function in this manual.
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M16C/6S Group
Interrupts
Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector. Figure 1.9.2 shows the interrupt vector.
MSB
LSB Low address Mid address 0000 High address 0000
Vector address (L)
Vector address (H)
0000
Figure 1.9.2. Interrupt Vector * Fixed Vector Tables The fixed vector tables are allocated to the addresses from FFFDC16 to FFFFF16. Table 1.9.1 lists the fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed vectors are used by the ID code check function. For details, refer to the section "flash memory rewrite disabling function". Table 1.9.1. Fixed Vector Tables Vector table addresses Remarks Reference Address (L) to address (H) Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction M16C/60, M16C/20 Overflow FFFE016 to FFFE316 Interrupt on INTO instruction series software If the contents of address manual BRK instruction FFFE416 to FFFE716 FFFE716 is FF16, program execution starts from the address shown by the vector in the relocatable vector table. Address match FFFE816 to FFFEB16 Address match interrupt Single step (Note) FFFEC16 to FFFEF16 Watchdog timer FFFF016 to FFFF316 Watchdog timer Oscillation stop and re-oscillation detection Clock generating circuit ________ DBC (Note) FFFF416 to FFFF716 (Reserved) FFFF816 to FFFFB16 Reset FFFFC16 to FFFFF16 Reset Note: Do not normally use this interrupt because it is provided exclusively for use by development support tools. Interrupt source
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Interrupts
* Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 1.9.2 lists the relocatable vector tables. Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses. Table 1.9.2. Relocatable Vector Tables
Interrupt source BRK instruction (Note 5) (Reserved) INT3 (Reserved) (Note 4) Timer B4, UART1 bus collision detect (Note 4) Timer B3, UART0 bus collision detect SI/O4, INT5 SI/O3, INT4 (Note 2) (Note 2) +16 to +19 (001016 to 001316) +20 to +23 (001416 to 001716) +24 to +27 (001816 to 001B16) +28 to +31 (001C16 to 001F16) +32 to +35 (002016 to 002316) +36 to +39 (002416 to 002716) +40 to +43 (002816 to 002B16) +44 to +47 (002C16 to 002F16) +48 to +51 (003016 to 003316) (Reserved) (Reserved) UART2 transmit, NACK2 (Note 3) UART2 receive, ACK2 (Note 3) UART0 transmit, NACK0 (Note 3) UART0 receive, ACK0 (Note 3) UART1 transmit, NACK1(Note 3) UART1 receive, ACK1 (Note 3) Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 (Reserved) (Reserved) (Reserved) INT0 INT1 INT2 +52 to +55 (003416 to 003716) +56 to +59 (003816 to 003B16) +60 to +63 (003C16 to 003F16) +64 to +67 (004016 to 004316) +68 to +71 (004416 to 004716) +72 to +75 (004816 to 004B16) +76 to +79 (004C16 to 004F16) +80 to +83 (005016 to 005316) +84 to +87 (005416 to 005716) +88 to +91 (005816 to 005B16) +92 to +95 (005C16 to 005F16) +96 to +99 (006016 to 006316) +100 to +103 (006416 to 006716) +104 to +107 (006816 to 006B16) +108 to +111 (006C 16 to 006F16) +112 to +115 (0070 16 to 007316) +116 to +119 (0074 16 to 007716) +120 to +123 (007816 to 007B16) +124 to +127 (007C16 to 007F16) +128 to +131 (008016 to 008316) Software interrupt (Note 5) to +252 to +255 (00FC16 to 00FF16) Vector address (Note 1) Address (L) to address (H) +0 to +3 (000016 to 000316) Software interrupt number 0 1 to 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 to 63 M16C/60, M16C/20 series software manual INT interrupt Timer Serial I/O DMAC Timer Serial I/O INT interrupt Serial I/O Serial I/O Reference M16C/60, M16C/20 series software manual INT interrupt
UART 2 bus collision detection DMA0 DMA1
Note 1: Address relative to address in INTB. Note 2: Set the IFSR register's IFSR6 and IFSR7 bits "0". Note 3: During I2C mode, NACK and ACK interrupts comprise the interrupt source. Note 4: Set the IFSR2A register's IFSR26 and IFSR27 bits "1". Note 5: These interrupts cannot be disabled using the I flag.
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M16C/6S Group
Interrupts
Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use the FLG register's I flag, IPL, and each interrupt control register's ILVL2 to ILVL0 bits to enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control register. Figure 1.9.3 shows the interrupt control registers.
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M16C/6S Group
Interrupts
Interrupt control register (Note 2)
Symbol U1BCNIC (Note 3) U0BCNIC (Note 3) BCNIC DM0IC, DM1IC S0TIC to S2TIC S0RIC to S2RIC TA0IC to TA4IC Address 0046 16 0047 16 004A16 004B16, 004C16 005116, 005316, 004F16 005216, 005416, 005016 005516 to 005916 After reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 RW RW
b7
b6
b5
b4
b3
b2
b1
b0
Bit symbol
ILVL0
Bit name
Interrupt priority level select bit
b2 b1 b0
Function
000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7
ILVL1
RW
ILVL2
RW RW (Note 1)
IR
Interrupt request bit
0 : Interrupt not requested 1 : Interrupt requested
(b7-b4)
No functions are assigned. When writing to these bits, write "0". The values in these bits when read are indeterminate.
Note 1: This bit can only be reset by writing "0" (Do not write "1"). Note 2: To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that register. For details, see the precautions for interrupts. Note 3: Use the IFSR2A register to select. Symbol INT3IC S4IC S3IC INT0IC to INT2IC Address 004416 004816 004916 005D16 to 005F16 After reset XX00X0002 XX00X0002 XX00X0002 XX00X0002
b7
b6
b5
b4
b3
b2
b1
b0
0
Bit symbol
ILVL0
Bit name
Interrupt priority level select bit
b2 b1 b0
Function
0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge (Notes 3, 4) 1 : Selects rising edge Must always be set to "0"
RW RW
ILVL1
RW
ILVL2
RW RW (Note 1) RW RW
IR
Interrupt request bit
POL
Polarity select bit
Reserved bit
(b7-b6)
No functions are assigned. When writing to these bits, write "0". The values in these bits when read are indeterminate.
RW
Note 1: This bit can only be reset by writing "0" (Do not write "1"). Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. For details, see the precautions for interrupts. Note 3: If the IFSR register's IFSRi bit (i = 0 to 5) is "1" (both edges), set the INTiIC register's POL bit to "0 "(falling edge). Note 4: Set the S3IC or S4IC register's POL bit to "0" (falling edge) when the IFSR register's IFSR6 bit = 0 (SI/O3 selected) or IFSR7 bit = 0 (SI/O4 selected), respectively.
Figure 1.9.3. Interrupt Control Registers
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Interrupts
I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to "1" (= enabled) enables the maskable interrupt. Setting the I flag to "0" (= disabled) disables all maskable interrupts.
IR Bit
The IR bit is set to "1" (= interrupt requested) when an interrupt request is generated. Then, when the interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is cleared to "0" (= interrupt not requested). The IR bit can be cleared to "0" in a program. Note that do not write "1" to this bit.
ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits. Table 1.9.3 shows the settings of interrupt priority levels and Table 1.9.4 shows the interrupt priority levels enabled by the IPL. The following are conditions under which an interrupt is accepted: * I flag = "1" * IR bit = "1" * interrupt priority level > IPL The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one another.
Table 1.9.3. Settings of Interrupt Priority Levels
ILVL2 to ILVL0 bits Interrupt priority level Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Low Priority order
Table 1.9.4. Interrupt Priority Levels Enabled by IPL
IPL 0002 0012 0102 0112 1002 1012 1102 1112 Enabled interrupt priority levels
0002 0012 0102 0112 1002 1012 1102 1112
Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled
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Interrupts
Interrupt Sequence
An interrupt sequence -- what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed -- is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. The CPU behavior during the interrupt sequence is described below. Figure 1.9.4 shows time required for executing the interrupt sequence. (1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading the address 0000016. Then it clears the IR bit for the corresponding interrupt to "0" (interrupt not requested). (2) The FLG register immediately before entering the interrupt sequence is saved to the CPU's internal temporary register(Note 1). (3) The I, D and U flags in the FLG register become as follows: The I flag is cleared to "0" (interrupts disabled). The D flag is cleared to "0" (single-step interrupt disabled). The U flag is cleared to "0" (ISP selected). However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is executed. (4) The CPU's internal temporary register (Note 1) is saved to the stack. (5) The PC is saved to the stack. (6) The interrupt priority level of the accepted interrupt is set in the IPL. (7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC. After the interrupt sequence is completed, the processor resumes executing instructions from the start address of the interrupt routine. Note: This register cannot be used by user.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CPU clock Address bus Data bus RD WR The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready to accept instructions. Address 000016
Interrupt information
Indeterminate Indeterminate Indeterminate
SP-2 SP-2 contents
SP-4 SP-4 contents
vec vec contents
vec+2 vec+2 contents
PC
Figure 1.9.4. Time Required for Executing Interrupt Sequence Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 55 of 190
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Interrupts
Interrupt Response Time
Figure 1.9.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when the instruction then executing is completed ((a) in Figure 1.9.5) and a time during which the interrupt sequence is executed ((b) in Figure 1.9.5).
Interrupt request generated
Interrupt request acknowledged Time
Instruction (a)
Interrupt sequence (b)
Instruction in interrupt routine
Interrupt response time
(a) A time from when an interrupt request is generated till when the instruction then executing is completed. The length of this time varies with the instruction being executed. The DIVX instruction requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register). (b) A time during which the interrupt sequence is executed. For details, see the table below. Note, however, that the values in this table must be increased 2 cycles for the DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt vector address SP value 16-Bit bus, without wait Even Even Odd Odd Even Odd Even Odd 18 cycles 19 cycles 19 cycles 20 cycles
8-Bit bus, without wait 20 cycles 20 cycles 20 cycles 20 cycles
Figure 1.9.5. Interrupt response time
Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in Table 1.9.5 is set in the IPL. Shown in Table 1.9.5 are the IPL values of software and special interrupts when they are accepted. Table 1.9.5. IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted Interrupt sources Watchdog timer
_________
Level that is set to IPL 7 Not changed
Software, address match, DBC, single-step
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Interrupts
Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure 1.9.6 shows the stack status before and after an interrupt request is accepted. The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Address MSB
Stack L SB
Address MSB
Stack L SB [SP] New SP value
m-4 m-3 m-2 m-1 m m+1 Content of previous stack Content of previous stack [SP] SPvalue before interrupt occurs
m-4 m-3 m-2 m-1 m m+1 FLGH
PC
L
PC
M
FLGL PCH
Content of previous stack Content of previous stack
Stack status before interrupt request is acknowledged
PCH : 4 high-order bits of PC PCM : 8 middle-order bits of PC PCL : 8 low-order bits of PC FLGH : 4 high-order bits of FLG FLGL : 8 low-order bits of FLG
Stack status after interrupt request is acknowledged
Figure 1.9.6. Stack Status Before and After Acceptance of Interrupt Request
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Interrupts
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP(Note), at the time of acceptance of an interrupt request, is even or odd. If the stack pointer (Note) is even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 1.9.7 shows the operation of the saving registers. Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated by the U flag. Otherwise, it is the ISP.
(1) SP contains even number
Address Stack Sequence in which order registers are saved
[SP] - 5 (Odd) [SP] - 4 (Even) [SP] - 3(Odd) [SP] - 2 (Even) [SP] - 1(Odd) [SP] (Even) Finished saving registers in two operations. FLGH PCL PCM FLGL PCH (1) Saved simultaneously, all 16 bits (2) Saved simultaneously, all 16 bits
(2) SP contains odd number
Address Stack Sequence in which order registers are saved
[SP] - 5 (Even) [SP] - 4(Odd) [SP] - 3 (Even) [SP] - 2(Odd) [SP] - 1 (Even) [SP] (Odd) Finished saving registers in four operations. FLGH PCL PCM FLGL PCH
(3) (4)
Saved, 8 bits at a time
(1) (2)
PCH : 4 high-order bits of PC PCM : 8 middle-order bits of PC PCL : 8 low-order bits of PC
FLGH : 4 high-order bits of FLG FLGL : 8 low-order bits of FLG
Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4.
Figure 1.9.7. Operation of Saving Register Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 58 of 190
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Interrupts
Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request. Return the other registers saved by a program within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.
Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request that has the highest priority is accepted. For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the highest priority interrupt accepted. The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 1.9.8 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine.
________
Reset > DBC > WDT > Peripheral function > Single step > Address match
Figure 1.9.8. Hardware Interrupt Priority
Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those requested. Figure 1.9.9 shows the circuit that judges the interrupt priority level.
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Interrupts
Priority level of each interrupt INT1
Level 0 (initial value)
High
Timer A3 Timer A1 UART1 bus collision INT3 INT2 INT0 Timer A4 Timer A2 UART0 bus collision UART1 reception, ACK1 UART0 reception, ACK0 UART2 reception, ACK2 DMA1 UART 2 bus collision SI/O4 Timer A0 UART1 transmission, NACK1 UART0 transmission, NACK0 UART2 transmission, NACK2 DMA0
Priority of peripheral function interrupts (if priority levels are same)
Low
SI/O3 IPL Interrupt request level resolution output to clock generating circuit (Fig.1.11.1)
I flag Address match Watchdog timer Oscillation stop and re-oscillation detection Power supply down detection DBC
Interrupt request accepted
Figure 1.9.9. Interrupts Priority Select Circuit Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 60 of 190
M16C/6S Group
Interrupts
______
INT Interrupt
_______
INTi interrupt (i=0 to 3) is triggered by the edges of external inputs. The edge polarity is selected using the IFSR register's IFSRi bit. Figure 1.9.10 shows the IFSR and IFSR2A registers.
Interrupt request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol IFSR
Bit symbol
Address 035F16
After reset 0016
Bit name
INT0 interrupt polarity switching bit INT1 interrupt polarity switching bit INT2 interrupt polarity switching bit INT3 interrupt polarity switching bit
Function
0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges (Note 1) (Note 1) (Note 1) (Note 1)
RW RW RW RW RW
IFSR0 IFSR1 IFSR2 IFSR3
(b5-b4) IFSR6 IFSR7
Nothing is assigned. When write, set to "0". When read, its content is interdeterminate. Interrupt request cause select bit (Note 2) Interrupt request cause select bit (Note 2) 0 : SI/O3 (Note 3) 1 : reserved 0 : SI/O4 1 : reserved
RW RW
Note 1: When setting this bit to "1" (= both edges), make sure the INT0IC to INT5IC register's POL bit is set to "0" (= falling edge). Note 2: Set this bit to "0" (= SI/O3, SI/O4) Note 3: When setting this bit to "0" (= SI/O3, SI/O4), make sure the S3IC and S4IC registers' POL bit is set to "0" (= falling edge).
Interrupt request cause select register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IFSR2A Bit symbol (b5-b0) IFSR26
Address 035E16
After reset 00XXXXXX2
Bit name
Function
RW
Nothing is assigned. When write, set to "0". When read, their contents are indeterminate. Interrupt request cause select bit Interrupt request cause select bit 0 : reserved 1 : UART0 bus collision detection 0 : reserved 1 : UART1 bus collision detection
RW RW
IFSR27
Figure 1.9.10. IFSR Register and IFSR2A Register
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Interrupts
Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0 to 3). Set the start address of any instruction in the RMADi register. Use the AIER register's AIER0 and AIER1 bits and the AIER2 register's AIER20 and AIER21 bits to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL. For address match interrupts, the value of the PC that is saved to the stack area varies depending on the instruction being executed (refer to Saving Registers). (The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one of the methods described below to return from the address match interrupt. * Rewrite the content of the stack and then use the REIT instruction to return. * Restore the stack to its previous state before the interrupt request was accepted by using the POP or similar other instruction and then use a jump instruction to return. Table 1.9.6 shows the value of the PC that is saved to the stack area when an address match interrupt request is accepted. Figure 1.9.11 shows the AIER, AIER2, and RMAD0 to RMAD3 registers. Table 1.9.6. Value of the PC that is saved to the stack area when an address match interrupt request is accepted
Instruction at the Address Indicated by the RMADi Register
* 16-bit op-code instruction * Instruction shown below among 8-bit operation code instructions ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B:S #IMM8,dest STNZ.B:S #IMM8,dest STZX.B:S #IMM81,#IMM82,dest CMP.B:S #IMM8,dest PUSHM src POPM dest JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (However, dest=A0 or A1) Value of the PC that is saved to the stack area
The address indicated by the RMADi register +2
Instructions other than the above
The address indicated by the RMADi register +1
Value of the PC that is saved to the stack area : Refer to 12.5.7 Saving Registers.
Table 1.9.7. Relationship Between Address Match Interrupt Sources and Associated Registers Address match interrupt sources Address match interrupt 0 Address match interrupt 1 Address match interrupt 2 Address match interrupt 3 Address match interrupt enable bit AIER0 AIER1 AIER20 AIER21 Address match interrupt register RMAD0 RMAD1 RMAD2 RMAD3
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Interrupts
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AIER Bit symbol
Address 000916 Bit name Address match interrupt 0 enable bit Address match interrupt 1 enable bit
After reset XXXXXX002 Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
RW RW RW
AIER0 AIER1
(b7-b2)
Nothing is assigned. When write, set to "0". When read, their contents are indeterminate.
Address match interrupt enable register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AIER2 Bit symbol
Address 01BB16 Bit name Address match interrupt 2 enable bit Address match interrupt 3 enable bit
After reset XXXXXX002 Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
RW RW RW
AIER20 AIER21
(b7-b2)
Nothing is assigned. When write, set to "0". When read, their contents are indeterminate.
Address match interrupt register i (i = 0 to 3)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol RMAD0 RMAD1 RMAD2 RMAD3
Address 001216 to 001016 001616 to 001416 01BA16 to 01B816 01BE16 to 01BC16
After reset X0000016 X0000016 X0000016 X0000016
Function Address setting register for address match interrupt Nothing is assigned. When write, set to "0". When read, their contents are indeterminate.
Setting range 0000016 to FFFFF16
RW RW
Figure 1.9.11. AIER Register, AIER2 Register and RMAD0 to RMAD3 Registers
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Interrupts
Precautions for Interrupts (1) Reading Address 0000016
* Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to "0". If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is cleared to "0". This causes a problem that the interrupt is canceled, or an unexpected interrupt is generated.
(2) SP Setting
* Set any value in the SP before accepting an interrupt. The SP is cleared to `000016' after reset. Therefore, if an interrupt is accepted before setting any value in the SP, the program may go out of control.
_____
(3) INT Interrupt
________
* Either an "L" level or an "H" level of at least 250 ns width is necessary for the signal input to the INT0 ________ through INT3 pins regardless of the CPU clock. ________ ________ * When the polarity of the INT0 to INT3 pins is changed, the IR bit is sometimes set to "1" (=interrupt requested). After changing the polarity, set the IR bit to "0" (=interrupt not requested). Figure ______ 1.9.11shows the procedure for changing the INT interrupt generate factor.
(4) Watchdog Timer Interrupt
* Initialize the watchdog timer after the watchdog timer interrupt occurs.
Set the I flag to "0" (=disable interrupt)
Set the ILVL2 to ILVL0 bits to '0002' (= level 0) (Disable INT interrupt) Set the POL bit Set the IR bit to "0" (=interrupt not requested) Set the ILVL2 to ILVL0 bits to '0012' (=level 1) to '1112' (=level 7) (Enable the accepting of INT interrupt request) Set the I flag to "1" (= enable interrupt) Note: Execute the setting above individually. Do not execute two or more settings at once (by one instruction).
______
Figure 1.9.12. Switching Procedure for INT Interrupt Request
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Interrupts
(5) Modifying Interrupt Control Register
* Each interrupt control register can only be modified while no interrupt requests corresponding to that register are generated. If interrupt requests managed by any interrupt control register are likely to occur, disable the interrupts before modifying the register. A sample program is shown below. To modify any interrupt control register after disabling interrupts, be careful with the instructions used. Modifying other than the IR bit If an interrupt request corresponding to that register is generated while executing the instruction, the IR bit may not be set to "1" (= interrupt requested), with the result that the interrupt request is ignored. If this presents a problem, use the following instructions to modify the register. Instructions to use: AND, OR, BCLR, BSET Modifying the IR bit Even when the IR bit is cleared to "0" (= interrupt not requested), it may not actually be cleared to "0" depending on the instruction used. Therefore, use the MOV instruction to clear the IR bit.
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Watchdog Timer
Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be performed when the watchdog timer underflows after reaching the terminal count can be selected using the PM12 bit of PM1 register. The PM12 bit can only be set to "1" (reset). Once this bit is set to "1", it cannot be set to "0" (watchdog timer interrupt) in a program. The pin, CPU and SFR initialized where the monitor timer underflows when the PM12 bit is "1" are the same as in software reset. When the main clock is selected for CPU clock, the divide-by-N value for the prescaler can be chosen to be 16 or 128. If a sub-clock is selected for CPU clock, the divide-by-N value for the prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can be calculated as given below. The period of watchdog timer is, however, subject to an error due to the prescaler. With main clock chosen for CPU clock Prescaler dividing (16 or 128) X Watchdog timer count (32768) Watchdog timer period = CPU clock
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog timer period is approx. 32.8 ms. The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset. Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start counting by writing to the WDTS register. In stop mode and wait mode, the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or state are released. Figure 1.10.1 shows the block diagram of the watchdog timer. Figure 1.10.2 shows the watchdog timerrelated registers. * Count source protective mode In this mode, a On-chip Oscillator clock is used for the watchdog timer count source. The watchdog timer can be kept being clocked even when CPU clock stops as a result of run-away. Before this mode can be used, the following register settings are required: (1) Set the PRC1 bit of PRCR register to "1" (enable writes to PM1 and PM2 registers). (2) Set the PM12 bit of PM1 register to "1" (reset when the watchdog timer underflows). (3) Set the PM22 bit of PM2 register to "1" (On-chip Oscillator clock used for the watchdog timer count source). (4) Set the PRC1 bit of PRCR register to "0" (disable writes to PM1 and PM2 registers). (5) Write to the WDTS register (watchdog timer starts counting).
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Watchdog Timer
Setting the PM22 bit to "1" results in the following conditions * The On-chip Oscillator starts oscillating, and the On-chip Oscillator clock becomes the watchdog timer count source. Watchdog timer count (32768) Watchdog timer period = on-chip oscillator clock * The CM10 bit of CM1 register is disabled against write. (Writing a "1" has no effect, nor is stop mode entered.) * The watchdog timer does not stop when in wait mode.
Prescaler
CM07 = 0 WDC7 = 0 PM12 = 0
1/16
CPU clock HOLD
1/128 1/2
CM07 = 0 WDC7 = 1
PM22 = 0
Watchdog timer interrupt request
CM07 = 1
PM22 = 1
Watchdog timer
PM12 = 1
Reset On-chip Oscillator clock Write to WDTS register Internal RESET signal ("L" active) Set to "7FFF16"
CM07: Bit in CM0 register WDC7: Bit in WDC register PM12: Bit in PM1 register PM22: Bit in PM2 register
Figure 1.10.1. Watchdog Timer Block Diagram
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol WDC Bit symbol (b4-b0) (b6-b5) WDC7
Address After reset 000F16 00XXXXXX2 Bit name High-order bit of watchdog timer Reserved bit Prescaler select bit Must set to 0 0 : Divided by 16 1 : Divided by 128 Function RW RO RW RW
Watchdog timer start register (Note)
b7 b0
Symbol WDTS
Address 000E16
After reset Indeterminate RW
Function
The watchdog timer is initialized and starts counting after a write instruction to WO this register. The watchdog timer value is always initialized to "7FFF16" regardless of whatever value is written. Note : Write to the WDTS register after the watchdog timer interrupt occurs.
Figure 1.10.2. WDC Register and WDTS Register Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 67 of 190
M16C/6S Group
DMAC
DMAC
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from the source address to the destination address. The DMAC uses the same data bus as used by the CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time after a DMA request is generated. Figure 1.11.1 shows the block diagram of the DMAC. Table 1.11.1 shows the DMAC specifications. Figures 1.11.2 to 1.11.4 show the DMAC-related registers.
Address bus
DMA0 source pointer SAR0(20) (addresses 002216 to 002016) DMA0 destination pointer DAR0 (20)
(addresses 002616 to 002416)
DMA0 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
DMA1 source pointer SAR1 (20) (addresses 003216 to 003016) DMA1 destination pointer DAR1 (20)
(addresses 003616 to 003416)
(addresses 002916, 002816) DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 forward address pointer (20) (Note)
(addresses 003916, 003816) DMA1 transfer counter TCR1 (16)
DMA latch high-order bits DMA latch low-order bits
Data bus low-order bits Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Figure 1.11.1. DMAC Block Diagram
A DMA request is generated by a write to the DMiSL register (i = 0-1)'s DSR bit, as well as by an interrupt request which is generated by any function specified by the DMiSL register's DMS and DSEL3-DSEL0 bits. However, unlike in the case of interrupt requests, DMA requests are not affected by the I flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt request can be accepted, DMA requests are always accepted. Furthermore, because the DMAC does not affect interrupts, the interrupt control register's IR bit does not change state due to a DMA transfer. A data transfer is initiated each time a DMA request is generated when the DMiCON register's DMAE bit = "1" (DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA transfer cycle, the number of transfer requests generated and the number of times data is transferred may not match. For details, refer to "DMA Requests". Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 68 of 190
M16C/6S Group
DMAC
Table 1.11.1. DMAC Specifications Item No. of channels Transfer memory space Specification 2 (cycle steal method) * From any address in the 1M bytes space to a fixed address * From a fixed address to any address in the 1M bytes space * From a fixed address to a fixed address 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________ ________
Maximum No. of bytes transferred DMA request factors (Note 1, Note 2)
Falling edge of INT0 or INT1 ________ ________ Both edge of INT0 or INT1 Timer A0 to timer A4 interrupt requests UART0 transfer, UART0 reception interrupt requests UART1 transfer, UART1 reception interrupt requests UART2 transfer, UART2 reception interrupt requests SI/O3, SI/O4 interrupt requests Software triggers Channel priority DMA0 > DMA1 (DMA0 takes precedence) Transfer unit 8 bits or 16 bits Transfer address direction forward or fixed (The source and destination addresses cannot both be in the forward direction.) Transfer mode *Single transfer Transfer is completed when the DMAi transfer counter (i = 0-1) underflows after reaching the terminal count. *Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the value of the DMAi transfer counter reload register and a DMA transfer is con tinued with it. DMA interrupt request generation timing When the DMAi transfer counter underflowed DMA startup Data transfer is initiated each time a DMA request is generated when the DMAiCON register's DMAE bit = "1" (enabled). DMA shutdown *Single transfer * When the DMAE bit is set to "0" (disabled) * After the DMAi transfer counter underflows *Repeat transfer When the DMAE bit is set to "0" (disabled) Reload timing for forward ad- When a data transfer is started after setting the DMAE bit to "1" (en abled), the forward address pointer is reloaded with the value of the dress pointer and transfer SARi or the DARi pointer whichever is specified to be in the forward counter direction and the DMAi transfer counter is reloaded with the value of the DMAi transfer counter reload register. Notes: 1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the interrupt control register. 2. The selectable causes of DMA requests differ with each channel. 3. Make sure that no DMAC-related registers (addresses 002016-003F16) are accessed by the DMAC.
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M16C/6S Group
DMAC
DMA0 request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DM0SL
Address 03B816
After reset 0016
Bit symbol DSEL0 DSEL1 DSEL2 DSEL3 (b5-b4) DMS
Bit name DMA request cause select bit Refer to note
Function
RW RW RW RW RW
Nothing is assigned. When write, set to "0". When read, its content is "0". DMA request cause expansion select bit Software DMA request bit 0: Basic cause of request 1: Extended cause of request A DMA request is generated by setting this bit to "1" when the DMS bit is "0" (basic cause) and the DSEL3 to DSEL0 bits are "00012" (software trigger). The value of this bit when read is "0" . RW
DSR
RW
Note: The causes of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the manner described below.
DSEL3 to DSEL0 0 0 0 02 0 0 0 12 0 0 1 02 0 0 1 12 0 1 0 02 0 1 0 12 0 1 1 02 0 1 1 12 1 0 0 02 1 0 0 12 1 0 1 02 1 0 1 12 1 1 0 02 1 1 0 12 1 1 1 02 1 1 1 12 DMS=0(basic cause of request) Falling edge of INT0 pin Software trigger Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 - - - UART0 transmit UART0 receive UART2 transmit UART2 receive - UART1 transmit DMS=1(extended cause of request) - - - - - - Two edges of INT0 pin - - - - - - - - -
Figure 1.11.2. DM0SL Register
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M16C/6S Group
DMAC
DMA1 request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DM1SL
Address 03BA16
After reset 0016
Bit symbol
Bit name DMA request cause select bit Refer to note
Function
RW RW RW RW RW
DSEL0 DSEL1 DSEL2 DSEL3 (b5-b4) DMS
Nothing is assigned. When write, set to "0". When read, its content is "0". DMA request cause expansion select bit Software DMA request bit 0: Basic cause of request 1: Extended cause of request A DMA request is generated by setting this bit to "1" when the DMS bit is "0" (basic cause) and the DSEL3 to DSEL0 bits are "00012" (software trigger). The value of this bit when read is "0" .
RW
DSR
RW
Note: The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the manner described below.
DSEL3 to DSEL0 0 0 0 02 0 0 0 12 0 0 1 02 0 0 1 12 0 1 0 02 0 1 0 12 0 1 1 02 0 1 1 12 1 0 0 02 1 0 0 12 1 0 1 02 1 0 1 12 1 1 0 02 1 1 0 12 1 1 1 02 1 1 1 12 DMS=0(basic cause of request) Falling edge of INT1 pin Software trigger Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 - - - UART0 transmit UART0 receive/ACK0 UART2 transmit UART2 receive/ACK2 - UART1 receive/ACK1 DMS=1(extended cause of request) - - - - - SI/O3 SI/O4 Two edges of INT1 - - - - - - - -
DMAi control register(i=0,1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DM0CON DM1CON Bit symbol DMBIT DMASL DMAS DMAE DSD DAD (b7-b6)
Address 002C16 003C16 Bit name Transfer unit bit select bit Repeat transfer mode select bit DMA request bit DMA enable bit Source address direction select bit (Note 2)
After reset 00000X002 00000X002 Function 0 : 16 bits 1 : 8 bits 0 : Single transfer 1 : Repeat transfer 0 : DMA not requested 1 : DMA requested 0 : Disabled 1 : Enabled 0 : Fixed 1 : Forward RW RW RW RW (Note 1) RW RW RW
Destination address 0 : Fixed direction select bit (Note 2) 1 : Forward
Nothing is assigned. When write, set to "0". When read, its content is "0".
Note 1: The DMAS bit can be set to "0" by writing "0" in a program (This bit remains unchanged even if "1" is written). Note 2: At least one of the DAD and DSD bits must be "0" (address direction fixed).
Figure 1.11.3. DM1SL Register, DM0CON Register, and DM1CON Registers Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 71 of 190
M16C/6S Group
DMAC
DMAi source pointer (i = 0, 1) (Note)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol SAR0 SAR1
Address 002216 to 002016 003216 to 003016
After reset Indeterminate Indeterminate
Function Set the source address of transfer
Setting range 0000016 to FFFFF16
RW RW
Nothing is assigned. When write, set "0". When read, these contents are "0". Note: If the DSD bit of DMiCON register is "0" (fixed), this register can only be written to when the DMAE bit of DMiCON register is "0" (DMA disabled). If the DSD bit is "1" (forward direction), this register can be written to at any time. If the DSD bit is "1" and the DMAE bit is "1" (DMA enabled), the DMAi forward address pointer can be read from this register. Otherwise, the value written to it can be read.
DMAi destination pointer (i = 0, 1)(Note)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol DAR0 DAR1
Address 002616 to 002416 003616 to 003416 Setting range
After reset Indeterminate Indeterminate RW RW
Function Set the destination address of transfer
0000016 to FFFFF16
Nothing is assigned. When write, set "0". When read, these contents are "0". Note: If the DAD bit of DMiCON register is "0" (fixed), this register can only be written to when the DMAE bit of DMiCON register is "0"(DMA disabled). If the DAD bit is "1" (forward direction), this register can be written to at any time. If the DAD bit is "1" and the DMAE bit is "1" (DMA enabled), the DMAi forward address pointer can be read from this register. Otherwise, the value written to it can be read.
DMAi transfer counter (i = 0, 1)
(b15) b7 (b8) b0 b7 b0
Symbol TCR0 TCR1
Address 002916, 002816 003916, 003816
After reset Indeterminate Indeterminate RW
Function Set the transfer count minus 1. The written value is stored in the DMAi transfer counter reload register, and when the DMAE bit of DMiCON register is set to "1" (DMA enabled) or the DMAi transfer counter underflows when the DMASL bit of DMiCON register is "1" (repeat transfer), the value of the DMAi transfer counter reload register is transferred to the DMAi transfer counter. When read, the DMAi transfer counter is read.
Setting range
000016 to FFFF16
RW
Figure 1.11.4. SAR0, SAR1, DAR0, DAR1, TCR0, and TCR1 Registers
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M16C/6S Group
DMAC
1. Transfer Cycles
The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source and destination ________ addresses of transfer. Furthermore, the bus cycle itself is extended by a software wait or RDY signal. (a) Effect of Source and Destination Addresses If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd address, the source read cycle consists of one more bus cycle than when the source address of transfer begins with an even address. Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer begins with an odd address, the destination write cycle consists of one more bus cycle than when the destination address of transfer begins with an even address. (b) Effect of Software Wait For memory or SFR accesses in which one or more software wait states are inserted, the number of bus cycles required for that access increases by an amount equal to software wait states. Figure 1.11.5 shows the example of the cycles for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating transfer cycles, take into consideration each condition for the source read and the destination write cycle, respectively. For example, when data is transferred in 16 bit units using an 8-bit bus ((2) in Figure 1.11.5), two source read bus cycles and two destination write bus cycles are required.
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M16C/6S Group
DMAC
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
BCLK Address bus RD signal WR signal Data bus
CPU use Source Destination Dummy cycle CPU use CPU use Source Destination Dummy cycle CPU use
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address
BCLK Address bus RD signal WR signal Data bus
CPU use Source Source + 1 Destination Dummy cycle CPU use CPU use Source Source + 1 Destination Dummy cycle CPU use
(3) When the source read cycle under condition (1) has one wait state inserted
BCLK Address bus RD signal WR signal Data bus
CPU use Source Destination Dummy cycle CPU use CPU use Source Destination Dummy cycle CPU use
(4) When the source read cycle under condition (2) has one wait state inserted
BCLK Address bus RD signal WR signal Data bus
CPU use Source Source + 1 Destination Dummy cycle CPU use CPU use Source Source + 1 Destination Dummy cycle CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 1.11.5. Transfer Cycles for Source Read Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 74 of 190
M16C/6S Group
DMAC
2. DMA Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible. Table 1.11.2 shows the number of DMA transfer cycles. Table 1.11.3 shows the Coefficient j, k. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Table 1.11.2. DMA Transfer Cycles Transfer unit 8-bit transfers (DMBIT= "1") 16-bit transfers (DMBIT= "0") Access address Even Odd Even Odd No. of read cycles 1 1 1 2 No. of write cycles 1 1 1 2
Table 1.11.3. Coefficient j, k
Internal ROM, RAM No wait j k 1 1 With wait 2 2 2 2 SFR 1-wait2 2-wait2 3 3
Notes: 1. Depends on the set value of CSE register 2. Depends on the set value of PM20 bit in P
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M16C/6S Group
DMAC
3. DMA Enable
When a data transfer starts after setting the DMAE bit in DMiCON register (i = 0, 1) to "1" (enabled), the DMAC operates as follows: (1) Reload the forward address pointer with the SARi register value when the DSD bit in DMiCON register is "1" (forward) or the DARi register value when the DAD bit of DMiCON register is "1" (forward). (2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value. If the DMAE bit is set to "1" again while it remains set, the DMAC performs the above operation. However, if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below. Step 1: Write "1" to the DMAE bit and DMAS bit in DMiCON register simultaneously. Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program. If the DMAi is not in an initial state, the above steps should be repeated.
4. DMA Request
The DMAC can generate a DMA request as triggered by the cause of request that is selected with the DMS and DSEL3 to DSEL0 bits of DMiSL register (i = 0, 1) on either channel. Table 1.13.4 shows the timing at which the DMAS bit changes state. Whenever a DMA request is generated, the DMAS bit is set to "1" (DMA requested) regardless of whether or not the DMAE bit is set. If the DMAE bit was set to "1" (enabled) when this occurred, the DMAS bit is set to "0" (DMA not requested) immediately before a data transfer starts. This bit cannot be set to "1" in a program (it can only be set to "0"). The DMAS bit may be set to "1" when the DMS or the DSEL3 to DSEL0 bits change state. Therefore, always be sure to set the DMAS bit to "0" after changing the DMS or the DSEL3 to DSEL0 bits. Because if the DMAE bit is "1", a data transfer starts immediately after a DMA request is generated, the DMAS bit in almost all cases is "0" when read in a program. Read the DMAE bit to determine whether the DMAC is enabled.
Table 1.11.4. Timing at Which the DMAS Bit Changes State DMAS bit of the DMiCON register DMA factor Timing at which the bit is set to "1" Timing at which the bit is set to "0"
Software trigger Peripheral function When the DSR bit of DMiCON register is set to "1" When the interrupt control register for the peripheral function that is selected by the DSEL3 to DSEL0 and DMS bits of DMiCON register has its IR bit set to "1" * Immediately before a data transfer starts * When set by writing "0" in a program
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M16C/6S Group
DMAC
Channel Priority and DMA Transfer Timing
If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS bit on each channel is set to "1" (DMA requested) at the same time. In this case, the DMA requests are arbitrated according to the channel priority, DMA0 > DMA1. The following describes DMAC operation when DMA0 and DMA1 requests are detected active in the same sampling period. Figure 1.11.6 shows an example of DMA transfer effected by external factors. In Figure 1.11.6, because DMA0 and DMA1 requests occurred at the same time, DMA0 which has higher channel priority is accepted first and a DMA transfer on it starts. When DMA0 finishes one transfer unit, it relinquishes control of the bus to the CPU, and when the CPU finishes one bus access, DMA1 starts a transfer next and after completion of one transfer unit, returns control of the bus to the CPU. Note that because there is only one DMAS bit on each channel, the number of times DMA is requested cannot be counted. Therefore, even if multiple DMA requests occurred before gaining control of the bus as in the case of DMA1 in Figure 1.11.6, the DMAS bit is set to "0" when control of the bus is gained and after completion of one transfer unit, control of the bus is returned to the CPU.
An example where DMA requests for external causes are detected active at the same
BCLK DMA0 DMA1 CPU INT0 DMA0 request bit INT1 DMA1 request bit Obtainment of the bus right
Figure 1.11.6. DMA Transfer by External Factors
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M16C/6S Group
Timers
Timers
Five 16-bit timers, each capable of operating independently of the others. The count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc. Figures 1.12.1 show block diagrams of timer A.
f2 PCLK0 bit = 0
1/2
f1 * Main clock * On-chip oscillator clock f1 or f2
PCLK0 bit = 1 1/8 1/4
f8 f32
f1 or f2 f8 f32 fC32
TCK1 to TCK0
00 01 10 11
00: Timer mode 10: One-shot timer mode 11: PWM mode
10 TMOD1 to TMOD0
Timer A0 interrupt Timer A0
TA0IN
Noise filter
01 00
01: Event counter mode
11 TA0TGH to TA0TGL TCK1 to TCK0 00 01 10 11
00: Timer mode 10: One-shot tiemr mode 11: PWM mode
10 01 00 TMOD1 to TMOD0
Timer A1 interrupt Timer A1
TA1IN
Noise filter
01: Event counter mode
11 TA1TGH to TA1TGL TCK1 to TCK0 00 01 10 11
00: Timer mode 10: One-shot timer mode 11: PWM mode
10 01 00 11 TMOD1 to TMOD0
Timer A2 interrupt Timer A2
TA2IN
Noise filter
01: Event counter mode
TA2TGH to TA2TGL
TCK1 to TCK0 00 01 10 11
00: Timer mode 10: One-shot timer mode 11: PWM mode
10 01 00 TMOD1 to TMOD0
Timer A3 interrupt Timer A3
TA3IN
Noise filter
01: Event counter mode
11 TA3TGH to TA3TGL TCK1 to TCK0
00 01 10 11
00: Timer mode 10: One-shot timer mode 11: PWM mode
10 TMOD1 to TMOD0
Timer A4 interrupt Timer A4
TA4IN
Noise filter
01 00
01: Event counter mode
11 TA4TGH to TA4TGL
Timer B2 overflow or underflow
TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register (i=0 to 4) TAiGH to TAiGL: Bits in ONSF register and TRGSR register
NOTES : 1. Be aware that TA0IN shares the pin with RXD2.
Figure 1.12.1. Timer A Configuration Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 78 of 190
M16C/6S Group
Timer A
Timer A
Figure 1.12.2 shows a block diagram of the timer A. Figures 1.12.3 to 1.12.5 show registers related to the timer A. The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the same function. Use the TMOD1 to TMOD0 bits of TAiMR register (i = 0 to 4) to select the desired mode. * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external device or overflows and underflows of other timers. * One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum count "000016." * Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively.
Select clock
High-Order Bits of Data Bus
Select Count Source * Timer f1 or f2 00 f8 01 f32 10
TCK1 to TCK0
:TMOD1 to TMOD0=00, MR2=0 * One-Shot Timer :TMOD1 to TMOD0=10 * Pulse Width Modulation:TMOD1 to TMOD0=11 TMOD1 to TMOD0, MR2 * Timer(gate function):TMOD1 to TMOD0=00, MR2=1 * Event counter:TMOD1 to TMOD0=01
Low-Order Bits of Data Bus 8 low-order bits Reload Register
8 highorder bits
TAiIN
Polarity Selector TAiS
00 00 01 11 01 0 1 Pulse Output MR2 TMOD1 to TMOD0
Counter Increment / decrement Always decrement except in event counter mode
TAj Overflow (1) TAk Overflow
(1)
10 11 TAiTGH to TAiTGL
To external trigger circuit
Decrement
TAiUD
TAiOUT Toggle Flip Flop
i=0 to 4 j=i-1, except j=4 if i=0 k=i+1, except k=0 if i=4 NOTES: 1. Overflow or underflow TCK1 to TCK0, TMOD1 to TMOC0, MR2 to MR1 : Bits in TAiMR register TAiTGH to TAiTGL : Bits in ONSF register if i=0 or bits in TRGSR register if i=1 to 4 TAiS : Bits in the TABSR register TAiUD : Bits in the UDF register TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Addresses 0387h - 0386h 0389h - 0388h 038Bh - 038Ah 038Dh - 038Ch 038Fh - 038Eh TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0
Figure 1.12.2. Timer A Block Diagram
Timer Ai mode register (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TA0MR to TA4MR
Address 039616 to 039A16
After reset 0016
Bit symbol
TMOD0
Bit name
Operation mode select bit
b1 b0
Function
0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode
RW RW RW RW RW RW RW RW RW
TMOD1
MR0 MR1 MR2 MR3 TCK0 TCK1
Function varies with each operation mode
Count source select bit
Function varies with each operation mode
Figure 1.12.3. TA0MR to TA4MR Registers Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 79 of 190
M16C/6S Group
Timer A
Timer Ai register (i= 0 to 4) (Note 1)
(b15) b7 (b8) b0 b7 b0
Symbol TA0 TA1 TA2 TA3 TA4 Function
Address 038716, 038616 038916, 038816 038B16, 038A16 038D16, 038C16 038F16, 038E16
After reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Setting range 000016 to FFFF16 000016 to FFFF16 RW RW RW WO
Mode Timer mode Event counter mode One-shot timer mode
Divide the count source by n + 1 where n = set value Divide the count source by FFFF16 - n + 1 where n = set value when counting up or by n + 1 when counting down (Note 5) Divide the count source by n where n = set value and cause the timer to stop
000016 to FFFF16 (Notes 2, 4)
Pulse width Modify the pulse width as follows: modulation PWM period: (2 16 - 1) / fj High level PWM pulse width: n / fj mode (16-bit PWM) where n = set value, fj = count source frequency Pulse width Modify the pulse width as follows: modulation PWM period: (2 8 - 1) x (m + 1)/ fj mode High level PWM pulse width: (m + 1)n / fj (8-bit PWM) where n = high-order address set value, m = low-order address set value, fj = count source frequency
000016 to FFFE16 (Note 3, 4) WO
0016 to FE16 (High-order address) 0016 to FF16 (Low-order address) WO (Note 3, 4)
Note 1: The register must be accessed in 16 bit units. Note 2: If the TAi register is set to `0000 16,' the counter does not work and timer Ai interrupt requests are not generated either. Furthermore, if "pulse output" is selected, no pulses are output from the TAiOUT pin. Note 3: If the TAi register is set to `0000 16,' the pulse width modulator does not work, the output level on the TAiOUT pin remains low, and timer Ai interrupt requests are not generated either. The same applies when the 8 high-order bits of the timer TAi register are set to `001 6' while operating as an 8-bit pulse width modulator. Note 4: Use the MOV instruction to write to the TAi register. Note 5: The timer counts pulses from an external device or overflows or underflows in other timers.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Address 038016
After reset 0016
Bit symbol TA0S TA1S TA2S TA3S TA4S
(b7-b5)
Bit name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag
Function 0 : Stops counting 1 : Starts counting
RW RW RW RW RW RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Up/down flag (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UDF
Address 038416
After reset 0016
Bit symbol TA0UD TA1UD TA2UD TA3UD TA4UD TA2P TA3P TA4P
Bit name Timer A0 up/down flag Timer A1 up/down flag Timer A2 up/down flag Timer A3 up/down flag Timer A4 up/down flag
Function 0 : Down count 1 : Up count Enabled by setting the TAiMR register's MR2 bit to "0" (= switching source in UDF register) during event counter mode.
RW RW RW RW RW RW
Timer A2 two-phase pulse 0 : two-phase pulse signal WO processing disabled signal processing select bit 1 : two-phase pulse signal processing enabled Timer A3 two-phase pulse WO (Notes 2, 3) signal processing select bit Timer A4 two-phase pulse signal processing select bit WO
Note 1: Use MOV instruction to write to this register. Note 2: Make sure the port direction bits for the TA2 IN to TA4I N and TA2 OUT to TA4 OUT pins are set to "0" (input mode). Note 3: When not using the two-phase pulse signal processing function, set the corresponding bit to "0" (TA2P and TA3P must be set "0").
Figure 1.12.4. TA0 to TA4 Registers, TABSR Register, and UDF Register Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 80 of 190
M16C/6S Group
Timer A
One-shot start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ONSF
Address 038216
After reset 0016
0 Bit symbol
TA0OS TA1OS TA2OS TA3OS TA4OS
Bit name Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag Reserved bit Timer A0 event/trigger select bit
Function The timer starts counting by setting this bit to "1" while the TMOD1 to TMOD0 bits of TAiMR register (i = 0 to 4) = `102' (= one-shot timer mode) and the MR2 bit of TAiMR register = "0" (=TAiOS bit enabled). When read, its content is "0". Should be set to "0".
b7 b6
RW RW RW RW RW RW RW
(b6)
TA0TGL TA0TGH
RW 0 0 : Input on TA0IN is selected (Note 1) 0 1 : TB2 overflow is selected (Note 2) 1 0 : TA4 overflow is selected (Note 2) RW 1 1 : TA1 overflow is selected (Note 2)
Note 1: Make sure the PD7_1 bit of PD7 register is set to "0" (= input mode). Note 2: Overflow or underflow
Trigger select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRGSR
Address 038316
After reset 0016
Bit symbol
TA1TGL
Bit name Timer A1 event/trigger select bit
Function
b1 b0
RW
TA1TGH TA2TGL
0 0 : Input on TA1IN is selected (Note 1) RW 1 0 : TA0 overflow is selected (Note 2) 1 1 : TA2 overflow is selected (Note 2) RW
(Note 3)
Timer A2 event/trigger select bit
1 0 : TA1 overflow is selected (Note 2) RW 1 1 : TA3 overflow is selected (Note 2)
(Note 3)
b3 b2
TA2TGH TA3TGL TA3TGH
RW
Timer A3 event/trigger select bit
b5 b4
1 0 : TA2 overflow is selected (Note 2) RW 1 1 : TA4 overflow is selected (Note 2) (Note 3) RW
b7 b6
TA4TGL TA4TGH
Timer A4 event/trigger select bit
0 0 : Input on TA4IN is selected (Note 1) RW 1 0 : TA3 overflow is selected (Note 2) 1 1 : TA0 overflow is selected (Note 2) RW
(Note 3)
Note 1: Make sure the port direction bits for the TA1IN to TA4IN pins are set to "0" (= input mode). Note 2: Overflow or underflow Note 3: Do not set cases which are not discribed.
Figure 1.12.5. ONSF Register, TRGSR Register, and CPSRF Register
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M16C/6S Group
Timer A
1. Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 1.12.1). Figure 1.12.6 shows TAiMR register in timer mode. Table 1.12.1. Specifications in Timer Mode Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Specification f1, f2, f8, f32 * Down-count * When the timer underflows, it reloads the reload register contents and continues counting 1/(n+1) n: set value of TAiMR register (i= 0 to 4) 000016 to FFFF16 Set TAiS bit of TABSR register to "1" (= start counting) Set TAiS bit to "0" (= stop counting) Timer underflow I/O port or gate input i2, 3 I/O port or pulse output Count value can be read by reading TAi register * When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next) * Gate function Counting can be started and stopped by an input signal to TAiIN pin * Pulse output function Whenever the timer underflows, the output polarity of TAiOUT pin is inverted. When not counting, the pin outputs a low.
Select function
Timer Ai mode register (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol TA0MR to TA4MR Bit symbol TMOD0 TMOD1 MR0
Address 039616 to 039A16 Bit name
After reset 0016 Function RW RW RW RW
Operation mode select bit Pulse output function select bit
b1 b0
0 0 : Timer mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin)
b4 b3
MR1
Gate function select bit
MR2
0 0 : Gate function not available } (TAiIN pin functions as I/O port) 01: 1 0 : Counts while input on the TAiIN pin is low (Note 2) 1 1 : Counts while input on the TAiIN pin is high (Note 2)
RW
RW RW RW RW
MR3 TCK0 TCK1
Must be set to "0" in timer mode Count source select bit
b7 b6
0 0 : f1 or f2 0 1 : f8 1 0 : f32 1 1 : Do not set
Note 1: TA0OUT pin is N-channel open drain output. Note 2: The port direction bit for the TAi IN pin must be set to "0" (= input mode). There are not TA2IN and TA3IN.
Figure 1.12.6. Timer Ai Mode Register in Timer Mode Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 82 of 190
M16C/6S Group
Timer A
2. Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timer A4 can count two-phase external signals. Table 1.12.2 lists specifications in event counter mode (when not processing two-phase pulse signal). Table 1.12.3 lists specifications in event counter mode (when processing two-phase pulse signal with the timer A4). Figure 1.12.7 shows TAiMR register in event counter mode (when not processing two-phase pulse signal). Figure 1.12.8 shows TA4MR registers in event counter mode (when processing two-phase pulse signal with the timer A4).
Table 1.12.2. Specifications in Event Counter Mode (when not processing two-phase pulse signal) Item Specification Count source * External signals input to TAiIN pin (i=0 to 4) (effective edge can be selected in program) timer Aj (j=i-1, except j=4 if i=0) overflows or underflows, timer Ak (k=i+1, except k=0 if i=4) overflows or underflows Count operation * Up-count or down-count can be selected by external signal or program * When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the timer continues counting without reloading. Divided ratio 1/ (FFFF16 - n + 1) for up-count 1/ (n + 1) for down-count n : set value of TAi register 000016 to FFFF16 Count start condition Set TAiS bit of TABSR register to "1" (= start counting) Count stop condition Set TAiS bit to "0" (= stop counting) Interrupt request generation timing Timer overflow or underflow TAiIN pin function I/O port or count source input i2, 3 TAiOUT pin function I/O port, pulse output, or up/down-count select input Read from timer Count value can be read by reading TAi register Write to timer * When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next) Select function * Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it * Pulse output function Whenever the timer underflows or underflows, the output polarity of TAiOUT pin is inverted . When not counting, the pin outputs a low.
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M16C/6S Group
Timer A
Timer Ai mode register (i=0 to 4) (When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
0
01
Symbol TA0MR to TA4MR Bit symbol TMOD0 TMOD1 MR0 Bit name
Address 039616 to 039A16
After reset 0016 Function RW RW RW RW RW
Operation mode select bit Pulse output function select bit
b1 b0
0 1 : Event counter mode (Note 1) 0 : Pulse is not output (TAiOUT pin functions as I/O port) 1 : Pulse is output (Note 2)
(TAiOUT pin functions as pulse output pin)
MR1 MR2 MR3 TCK0 TCK1
Count polarity select bit (Note 3) Up/down switching cause select bit
0 : Counts external signal's falling edge RW 1 : Counts external signal's rising edge 0 : UDF register 1 : Input signal to TAiOUT pin (Note 4) RW RW RW RW
Must be set to "0" in event counter mode Count operation type select bit 0 : Reload type 1 : Free-run type
Can be "0" or "1" when not using two-phase pulse signal processing
Note 1: During event counter mode, the count source can be selected using the ONSF and TRGSR registers. Note 2: TA0OUT pin is N-channel open drain output. Note 3: Effective when the TAiGH and TAiGL bits of ONSF or TRGSR register are `002' (TAiIN pin input). Note 4: Count down when input on TAiOUT pin is low or count up when input on that pin is high. The port direction bit for TAiOUT pin must be set to "0" (= input mode).
Figure 1.12.7. TAiMR Register in Event Counter Mode (when not using two-phase pulse signal processing)
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M16C/6S Group
Timer A
Table 1.12.3. Specifications in Event Counter Mode (when processing two-phase pulse signal with timer A4) Item Specification Count source * Two-phase pulse signals input to TAiIN or TAiOUT pins (i = 4) Count operation * Up-count or down-count can be selected by two-phase pulse signal * When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the timer continues counting without reloading. Divide ratio 1/ (FFFF16 - n + 1) for up-count 1/ (n + 1) for down-count n : set value of TAi register 000016 to FFFF16 Count start condition Set TAiS bit of TABSR register to "1" (= start counting) Count stop condition Set TAiS bit to "0" (= stop counting) Interrupt request generation timing Timer overflow or underflow TAiIN pin function Two-phase pulse input TAiOUT pin function Two-phase pulse input Read from timer Count value can be read by reading timer A4 register Write to timer * When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TAi register is written to reload register (Transferred to counter when reloaded next) Select function * Multiply-by-4 processing operation (timer A4) If the phase relationship is such that TAkIN(k=4) pin goes "H" when the input signal on TAkOUT pin is "H", the timer counts up rising and falling edges on TAkOUT and TAkIN pins. If the phase relationship is such that TAkIN pin goes "L" when the input signal on TAkOUT pin is "H", the timer counts down rising and falling edges on TAkOUT and TAkIN pins.
TAkOUT
Count up all edges Count down all edges
TAkIN (k=3,4)
Count up all edges Count down all edges
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M16C/6S Group
Timer A
Timer Ai Mode Register (i=4) (When Using Two-Phase Pulse Signal Processing)
b7 b6 b5 b4 b3 b2 b1 b0
010001
Symbol TA4MR
Address 039Ah
After Reset 00h
Bit Symbol
TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1
Bit Name
Operation Mode Select Bit
b1 b0
Function
0 1 : Event counter mode
RW RW RW RW RW RW RW RW RW
To use two-phase pulse signal processing, set this bit to "0". To use two-phase pulse signal processing, set this bit to "0". To use two-phase pulse signal processing, set this bit to "1". To use two-phase pulse signal processing, set this bit to "0". Count Operation Type Select Bit Two-Phase Pulse Signal Processing Operation Select Bit (1, 2) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation
NOTES: 1. No matter how this bit is set, timer A4 always operates in x4 processing mode. 2. If two-phase pulse signal processing is desired, following register settings are required: * Set the TAiP bit in the UDF register to "1" (two-phase pulse signal processing function enabled). * Set the TAiTGH and TAiTGL bits in the TRGSR register to "00b" (TAiIN pin input). * Set the port direction bits for TAiIN and TAiOUT to "0" (input mode)
Figure 1.12.8. TA4MR Registers in Event Counter Mode (when using two-phase pulse signal processing with timer A4)
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M16C/6S Group
Timer A
3. One-shot Timer Mode
In one-shot timer mode, the timer is activated only once by one trigger. (See Table 1.12.4.) When the trigger occurs, the timer starts up and continues operating for a given period. Figure 1.12.10 shows the TAiMR register in one-shot timer mode. Table 1.12.4. Specifications in One-shot Timer Mode Item Count source Count operation Specification f1, f2, f8, f32 * Down-count * When the counter reaches 000016, it stops counting after reloading a new value * If a trigger occurs when counting, the timer reloads a new count and restarts counting 1/n n : set value of TAi register 000016 to FFFF16 However, the counter does not work if the divide-by-n value is set to 000016. TAiS bit of TABSR register = "1" (start counting) and one of the following triggers occurs. * External trigger input from the TAiIN pin * timer Aj (j=i-1, except j=4 if i=0) overflow or underflow, timer Ak (k=i+1, except k=0 if i=4) overflow or underflow * The TAiOS bit of ONSF register is set to "1" (= timer starts) * When the counter is reloaded after reaching "000016" * TAiS bit is set to "0" (= stop counting) When the counter reaches "000016" I/O port or trigger input I/O port or pulse output An indeterminate value is read by reading TAi register * When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next) * Pulse output function The timer outputs a low when not counting and a high when counting.
Divide ratio Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function TAiOUT pin function Read from timer Write to timer
Select function
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M16C/6S Group
Timer A
Timer Ai mode register (i=0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
0
10
Symbol TA0MR to TA4MR Bit symbol TMOD0 TMOD1 MR0
Address 39616 to 039A16 Bit name
After reset 0016 Function RW RW RW
Operation mode select bit Pulse output function select bit
b1 b0
1 0 : One-shot timer mode
0 : Pulse is not output (TAiOUT pin functions as I/O port) RW 1 : Pulse is output (Note 1) (TAiOUT pin functions as a pulse output pin)
0 : Falling edge of input signal to TAiIN pin (Note 3) 1 : Rising edge of input signal to TAiIN pin (Note 3) RW
MR1 MR2
External trigger select bit (Note 2) Trigger select bit
0 : TAiOS bit is enabled 1 : Selected by TAiTGH to TAiTGL bits
RW RW RW RW
MR3 TCK0 TCK1
Must be set to "0" in one-shot timer mode Count source select bit
b7 b6
0 0 : f1 or f2 0 1 : f8 1 0 : f32 1 1 : Do not set
Note 1: TA0OUT pin is N-channel open drain output. Note 2: Effective when the TAiGH and TAiGL bits of ONSF or TRGSR register are `00 2' (TAi IN pin input). Note 3: The port direction bit for the TAi IN pin must be set to "0" (= input mode). There are not TA2IN and TA3IN.
Figure 1.12.10. TAiMR Register in One-shot Timer Mode
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M16C/6S Group
Timer A
4. Pulse Width Modulation (PWM) Mode
In PWM mode, the timer outputs pulses of a given width in succession (see Table 1.12.5). The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 1.12.11 shows TAiMR register in pulse width modulation mode. Figures 1.12.12 and 1.12.13 show examples of how a 16-bit pulse width modulator operates and how an 8-bit pulse width modulator operates. Table 1.12.5. Specifications in PWM Mode
Item
Count source Count operation
Specification
f1, f2, f8, f32 * Down-count (operating as an 8-bit or a 16-bit pulse width modulator) * The timer reloads a new value at a rising edge of PWM pulse and continues counting * The timer is not affected by a trigger that occurs during counting * High level width n / fj n : set value of TAi register (i=o to 4) 16-1) / fj fixed * Cycle time (2 fj: count source frequency (f1, f2, f8, f32) * High level width n x (m+1) / fj n : set value of TAiMR register high-order address * Cycle time (28-1) x (m+1) / fj m : set value of TAiMR register low-order address * TAiS bit of TABSR register is set to "1" (= start counting) * The TAiS bit = 1 and external trigger input from the TAiIN pin * The TAiS bit = 1 and one of the following external triggers occurs Timer Aj (j=i-1, except j=4 if i=0) overflow or underflow, Timer Ak (k=i+1, except k=0 if i=4) overflow or underflow TAiS bit is set to "0" (= stop counting) PWM pulse goes "L" I/O port or trigger input Pulse output An indeterminate value is read by reading TAi register * When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter * When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next)
16-bit PWM 8-bit PWM Count start condition
Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer
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M16C/6S Group
Timer A
Timer Ai mode register (i= 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
11
1
Symbol TA0MR to TA4MR Bit symbol TMOD0 TMOD1 MR0 MR1 MR2
Address 039616 to 039A16
After reset 0016 Function RW RW (Note 1) RW RW
Bit name Operation mode select bit
b1 b0
1 1 : PWM mode
Must be set to "1" in PWM mode External trigger select bit (Note 2) Trigger select bit
0: Falling edge of input signal to TAiIN pin(Note 3) RW 1: Rising edge of input signal to TAiIN pin(Note 3)
0 : TAiOS bit is enabled 1 : Selected by TAiTGH to TAiTGL bits
0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator
b7 b6
RW
MR3
16/8-bit PWM mode select bit Count source select bit
RW RW RW
TCK0 TCK1
0 0 : f1 or f2 0 1 : f8 1 0 : f32 1 1 : Do not set
Note 1: TA0OUT pin is N-channel open drain output. Note 2: Effective when the TAiGH and TAiGL bits of ONSF or TRGSR register are `00 2' (TAi IN pin input). Note 3: The port direction bit for the TAi IN pin must be set to "0" (= input mode). There are not TA2IN and TA3IN.
Figure 1.12.11. TAiMR Register in PWM Mode
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M16C/6S Group
Timer A
1 / fi X (2 16 - 1)
Count source
Input signal to TA iIN pin
"H" "L"
Trigger is not generated by this signal 1 / fj X n
PWM pulse output from TA iOUT pin IR bit of TAiIC register
"H" "L" "1" "0"
fj : Frequency of count source (f1, f2, f8, f32) Set to "0" upon accepting an interrupt request or by writing in program i = 0 to 4 Note 1: n = 000016 to FFFE16. Note 2: This timing diagram is for the case where the TAi register is `0003 16,' the TAiGH and TAiGL bits of ONSF or TRGSR register = `00 2' (TAi IN pin input), the MR1 bit of TAiMR register = 1 (rising edge), and the MR2 bit of TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).
Figure 1.12.12. Example of 16-bit Pulse Width Modulator Operation
1 / fj X (m + 1) X (2 8 - 1) Count source (Note1)
Input signal to TA iIN pin
"H" "L"
1 / fj X (m + 1) Underflow signal of 8-bit prescaler (Note2) "L"
"H"
1 / fj X (m + 1) X n PWM pulse output from TA iOUT pin
"H" "L" "1" "0"
IR bit of TAiIC register
fj : Frequency of count source (f1, f2, f8, f32) i = 0 to 4
Set to "0" upon accepting an interrupt request or by writing in program
Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FF16; n = 0016 to FE16. Note 4: This timing diagram is for the case where the TAi register is `0202 16,' the TAiGH and TAiGL bits of ONSF or TRGSR register = `002' (TAi IN pin input), the MR1 bit of TAiMR register = 0 (falling edge), and the MR2 bit of TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).
Figure 1.12.13. Example of 8-bit Pulse Width Modulator Operation Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 91 of 190
M16C/6S Group
Serial I/O
Serial I/O
Serial I/O is configured with five channels: UART0 to UART2, SI/O3 and SI/O4.
UARTi (i=0 to 2)
UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 1.13.1 shows the block diagram of UARTi. Figures 1.13.2 shows the block diagram of the UARTi transmit/receive. UARTi has the following modes: * Clock synchronous serial I/O mode * Clock asynchronous serial I/O mode (UART mode). * Special mode 1 (I2C mode) * Special mode 2 Figures 1.13.3 to 1.13.8 show the UARTi-related registers. Refer to tables listing each mode for register setting.
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M16C/6S Group
Serial I/O
1/2
f2SIO f1SIO
0 1
PCLK1 f1SIO or f2SIO f8SIO 1/4 f32SIO TXD polarity reversing circuit
Main clock or on-chip oscillator clock
1/8
(UART0)
RXD0
RXD polarity reversing circuit 1/16 UART reception SMD2 toSMD0 010, 100, 101, 110 Clock synchronous type 001 U0BRG register
TXD0
Clock source selection
CLK1 to CLK0 f1SIO or f2SIO 00h 01h f8SIO 10h f32SIO 0 1 External CKDIR Internal
Reception control circuit
Receive clock
Transmit/ receive unit
1 / (n0+1)
1/16
UART transmission 010, 100, 101, 110 Clock synchronous type 001 Clock synchronous type (when internal clock is selected) 0 1
Transmission control circuit
Transmit clock
1/2
CKPOL
CLK0
CLK polarity reversing circuit
Clock synchronous type (when internal clock is selected)
Clock synchronous CKDIR type (when external clock is selected)
CTS/RTS disabled CTS/RTS selected
CTS0 / RTS0
RTS0
VSS 0 RCSP 1 0 CTS/RTS disabled
1 CRS 0 1
CTS0
CRD
CTS0 from UART1
n0: Values set to the U0BRG register PCLK1: Bit in the PCLKR register SMD2 to SMD0, CKDIR: Bits in U0MR register CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U0C0 register CLKMD0, CLKMD1, RCSP: Bits in UCON register
1/2 1/2
f2SIO f1SIO
0 1
PCLK1 f1SIO or f2SIO f8SIO 1/4 f32SIO TXD polarity reversing circuit
Main clock or on-chip oscillator clock
1/8
(UART1)
RXD1
RXD polarity reversing circuit 1/16
TXD1
UART reception SMD2 to SMD0 010, 100, 101, 110 Clock synchronous type 001 Reception control circuit
Clock source selection CLK1 to CLK0 CKDIR 00 Internal f1SIO or f2SIO 01 0 f8SIO 10 f32SIO 1 External
Receive clock
Transmit/ receive unit
U1BRG register
1 / (n1+1)
1/16
UART transmission 010, 100, 101, 110 Clock synchronous type 001 Clock synchronous type (when internal clock is selected) 0 1 CKDIR Transmission control circuit
Transmit clock
1/2
Clock synchronous type (when external clock is selected)) CKPOL Clock synchronous type (when internal clock is selected)
CLK1
CLK polarity reversing circuit Clock output pin select
0
CLKMD0
1
CTS1 / RTS1/ CTS0 / CLKS1
1 CTS/RTS selected CTS/RTS disabled CRS 1 0 CLKMD1 0 0 CRD RCSP VSS 1 CTS/RTS disabled 0 1
RTS1 CTS1
CTS0 from UART0
n1: Values set to the U1BRG register PCLK1: Bit in the PCLKR register SMD2 to SMD0, CKDIR: Bits in U1MR register CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U1C0 register CLKMD0, CLKMD1, RCSP: Bits in UCON register
1/2
f2SIO f1SIO
0 1
PCLK1 f1SIO or f2SIO f8SIO 1/4 f32SIO TXD polarity reversing circuit (1)
Main clock or on-chip oscillator clock
1/8
(UART2)
RXD2
RXD polarity reversing circuit 1/16
TXD2
UART reception SMD2 to SMD0 010, 100, 101, 110 Clock synchronous type 001 Reception control circuit
Clock source selection CLK1 to CLK0 CKDIR 00 Internal f1SIO or f2SIO 01 0 f8SIO 10 f32SIO External
Receive clock
Transmit/ receive unit
U2BRG register
1 / (n2+1)
UART transmission 1/16 010, 100, 101, 110 Clock synchronous type 001 Clock synchronous type (when internal clock is selected) 0
Transmission control circuit
Transmit clock
1/2
CTS/RTS disabled CTS/RTS selected
CKDIR
CTS2 / RTS2
RTS2
VSS 1 0 CTS/RTS disabled
1 CRS 0
CTS2
CRD
n2: Values set to the U2BRG register PCLK1: Bit in the PCLKR register SMD2 to SMD0, CKDIR: Bits in U2MR register CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U2C0 register CLKMD0, CLKMD1, RCSP: Bits in UCON register
NOTES : 1. UART2 is the N-channel open-drain output. Cannot be set to the CMOS output. 2. UART2 does not have CLK2 port. So CKDIR must not be set "1."
Figure 1.13.1. UARTi Block Diagram Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 93 of 190
M16C/6S Group
Serial I/O
IOPOL
RXDi
RXD data reverse circuit
No reverse
0 1
Reverse Clock synchronous type
STPS
1SP
PRYE
PAR disabled
Clock synchronous type
UART (7 bits) UART (8 bits)
UART(7 bits)
0
SP 2SP SP
PAR
0 1
PAR enabled
0 1
0
0
UARTi receive register
1
1 SMD2 to SMD0 UART (9 bits)
UART
Clock synchronous type
1
UART (8 bits) UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiRB register
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D8
D7
UART (8 bits) UART (9 bits)
D6
D5
D4
D3
D2
D1
D0
UiTB register
STPS
2SP
PRYE
PAR enabled
SMD2 to SMD0 UART
UART
(9 bits)
Clock synchronous type
1
SP SP
PAR
1
1 0
1
1
0
1SP
0
PAR disabled
Clock synchronous type
0
UART (7 bits) UART (8 bits)
Clock synchronous type
0
UART(7 bits)
Error signal output disable
UARTi transmit register
0
Error signal output circuit
IOPOL 0
No reverse
TXDi
i=0 to 2 SP: Stop bit PAR: Parity bit SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in UiMR register UiERE: Bit in UiC1 register
UiERE 1
1
TXD data reverse circuit
Error signal output enable
Reverse
Figure 1.13.2. UARTi Transmit/Receive Unit
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M16C/6S Group
Serial I/O
UARTi transmit buffer register (i=0 to 2)(Note)
(b15) b7 (b8) b0 b7 b0
Symbol U0TB U1TB U2TB
Address 03A316-03A216 03AB16-03AA16 037B16-037A16
After reset Indeterminate Indeterminate Indeterminate Function RW WO
Transmit data Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Note: Use MOV instruction to write to this register.
UARTi receive buffer register (i=0 to 2)
(b15) b7 (b8) b0 b7 b0
Symbol U0RB U1RB U2RB
Address 03A716-03A616 03AF16-03AE16 037F16-037E16
After reset Indeterminate Indeterminate Indeterminate
Bit symbol (b7-b0) (b8) (b10-b9) ABT OER FER PER SUM
Bit name Receive data (D7 to D0) Receive data (D8)
Function
RW RO RO
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". Arbitration lost detecting flag (Note 2) 0 : Not detected 1 : Detected RW RO RO RO
Overrun error flag (Note 1) 0 : No overrun error 1 : Overrun error found Framing error flag (Note 1) Parity error flag (Note 1) Error sum flag (Note 1) 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found
RO
Note 1: When the UiMR register's SMD2 to SMD0 bits = "000 2" (serial I/O disabled) or the UiC1 register's RE bit = "0" (reception disabled), all of the SUM, PER, FER and OER bits are set to "0" (no error). The SUM bit is set to "0" (no error) when all of the PER, FER and OER bits = "0" (no error). Also, the PER and FER bits are set to "0" by reading the lower byte of the UiRB register. Note 2: The ABT bit is set to "0" by writing "0" in a program. (Writing "1" has no effect.)
UARTi bit rate generator (i=0 to 2)(Notes 1, 2)
b7 b0
Symbol U0BRG U1BRG U2BRG
Address 03A116 03A916 037916 Function
After reset Indeterminate Indeterminate Indeterminate Setting range 0016 to FF16 RW WO
Assuming that set value = n, UiBRG divides the count source by n + 1 Note 1: Write to this register while serial I/O is neither transmitting nor receiving. Note 2: Use MOV instruction to write to this register.
Figure 1.13.3. U0TB to U2TB Register, U0RB to U2RB Register, and U0BRG to U2BRG Register
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Serial I/O
UARTi transmit/receive mode register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0MR to U2MR Bit symbol SMD0 SMD1 SMD2
Address 03A016, 03A816, 037816
After reset 0016 Function
Bit name Serial I/O mode select bit (Note 2)
b2 b1 b0
RW RW RW RW RW RW RW RW RW
0 0 0 : Serial I/O disabled 0 0 1 : Clock synchronous serial I/O mode (Note 3) 0 1 0 : I2C mode 1 0 0 : UART mode transfer data 7 bits long 1 0 1 : UART mode transfer data 8 bits long 1 1 0 : UART mode transfer data 9 bits long Must not be set except above 0 : Internal clock 1 : External clock (Note 1) 0 : One stop bit 1 : Two stop bits 0 : Odd parity 1 : Even parity (Note 4)
CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit
Odd/even parity select bit Effective when PRYE = 1
PRYE IOPOL
Parity enable bit TxD, RxD I/O polarity reverse bit
0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse
Note 1: Set the corresponding port direction bit for each CLKi pin to "0" (input mode). Note 2: To receive data, set the corresponding port direction bit for each RxDi pin to "0" (input mode). Note 3: Set the corresponding port direction bit for SCL and SDA pins to "0" (input mode). Note 4: Set "0" to select internal clock of UART2.
UARTi transmit/receive control register 0 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0C0 to U2C0
Address After reset 03A416, 03AC16, 037C16 000010002
Bit symbol CLK0 CLK1 CRS
Bit name BRG count source select bit
b1 b0
Function 0 0 : f1SIO or f2SIO is selected 0 1 : f8SIO is selected 1 0 : f32SIO is selected 1 1 : Must not be set Effective when CRD = 0 0 : CTS function is selected (Note 1) 1 : RTS function is selected
RW RW RW
CTS/RTS function select bit (Note 4)
RW
TXEPT
Transmit register empty 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register flag (transmission completed) CTS/RTS disable bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60, P64 and P73 can be used as I/O ports) 0 : TxDi/SDAi and SCLi pins are CMOS output 1 : TxDi/SDAi and SCLi pins are N-channel open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge
RO
CRD
RW
NCH CKPOL
Data output select bit (Note 2) CLK polarity select bit
RW
RW
UFORM Transfer format select bit 0 : LSB first (Note 3) 1 : MSB first
RW
Note 1: Set the corresponding port direction bit for each CTSi pin to "0" (input mode). Note 2: TXD2/SDA2 are N-channel open-drain output. Cannot be set to the CMOS output. NCH bit of U2C0 register is effective in an output set up of SCL2 pin. Note 3: Effective for clock synchronous serial I/O mode and UART mode transfer data 8 bits long. Note 4: CTS1/RTS1 can be used when the UCON register's CLKMD1 bit = "0" (only CLK1 output) and the UCON register's RCSP bit = "0" (CTS0/RTS0 not separated).
Figure 1.13.4. U0MR to U2MR Register and U0C0 to U2C0 Register Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 96 of 190
M16C/6S Group
Serial I/O
UARTi transmit/receive control register 1 (i=0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0C1, U1C1
Address 03A516,03AD16
After reset 000000102
Bit symbol TE TI RE RI
Bit name Transmit enable bit Transmit buffer empty flag Receive enable bit Receive complete flag
Function 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in UiTB register 1 : No data present in UiTB register 0 : Reception disabled 1 : Reception enabled 0 : No data present in UiRB register 1 : Data present in UiRB register
RW
RW RO RW RO
(b5-b4) UiLCH UiERE
Nothing is assigned. When write, set "0". When read, these contents are "0". Data logic select bit Error signal output enable bit 0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabled RW RW
NOTES: 1. The UiLCH bit is enabled when the SMD2 to SMD0 bits in the UiMR register are set to "001b" (clock synchronous serial I/O mode), "100b" (UART mode, 7-bit transfer data), or "101b" (UART mode, 8-bit transfer data). Set this bit to "0" when the SMD2 to SMD0 bits are set to "010b" (I2C mode) or "110b" (UART mode, 9-bit transfer data).
UART2 transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2C1
Address 037D16
After reset 000000102
Bit symbol TE TI RE RI
Bit name Transmit enable bit Transmit buffer empty flag Receive enable bit Receive complete flag
Function 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in U2TB register 1 : No data present in U2TB register 0 : Reception disabled 1 : Reception enabled 0 : No data present in U2RB register 1 : Data present in U2RB register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabled
RW
RW RO RW RO RW RW RW RW
U2IRS UART2 transmit interrupt cause select bit U2RRM UART2 continuous receive mode enable bit U2LCH Data logic select bit U2ERE Error signal output enable bit
NOTES: 1. The U2LCH bit is enabled when the SMD2 to SMD0 bits in the U2MR registerare set to "001b" (clock synchronous serial I/O mode), "100b" (UART mode, 7-bit transfer data), or "101b" (UART mode, 8-bit transfer data). Set this bit to "0" when the SMD2 to SMD0 bits are set to "010b" (I2C mode) or "110b" (UART mode, 9-bit transfer data).
Figure 1.13.5. U0C1 to U2C1 Registers
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M16C/6S Group
Serial I/O
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UCON
Address 03B016
After reset X00000002
Bit symbol U0IRS
Bit name UART0 transmit interrupt cause select bit UART1 transmit interrupt cause select bit
Function 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enable 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Effective when CLKMD1 = "1" 0 : Clock output from CLK1 1 : Clock output from CLKS1 0 : CLK output is only CLK1 1 : Transfer clock output from multiple pins function selected 0 : CTS/RTS shared pin 1 : CTS/RTS separated (CTS0 supplied from the P64 pin)
RW
RW
U1IRS
RW RW RW RW
U0RRM UART0 continuous receive mode enable bit U1RRM UART1 continuous receive mode enable bit CLKMD0 UART1 CLK/CLKS select bit 0 CLKMD1 UART1 CLK/CLKS select bit 1 (Note) RCSP Separate UART0 CTS/RTS bit
RW
RW
(b7)
Nothing is assigned. When write, set "0". When read, its content is indeterminate.
Note: When using multiple transfer clock output pins, make sure the following conditions are met: U1MR register's CKDIR bit = "0" (internal clock)
UART2 special mode register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
Symbol Address U0SMR to U2SMR 036F16, 037316, 037716 Bit symbol IICM ABC BBS
After reset X00000002
Bit name I2C mode select bit Arbitration lost detecting flag control bit Bus busy flag Reserved bit 0 : Other than I 2C mode 1 : I 2C mode 0 : Update per bit 1 : Update per byte
Function
RW
RW RW RW
(Note1)
0 : STOP condition detected 1 : START condition detected (busy) Set to "0"
(b3-b6)
RW
Nothing is assigned. When write, set "0". When read, its content is indeterminate. (b7) Note 1: The BBS bit is set to "0" by writing "0" in a program. (Writing "1" has no effect.).
Figure 1.13.6. UCON Register and U0SMR to U2SMR Registers
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M16C/6S Group
Serial I/O
UARTi special mode register 2 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address U0SMR2 to U2SMR2 036E16, 037216, 037616 Bit symbol IICM2 CSC SWC ALS STAC SWC2 SDHI
After reset X00000002
Bit name I 2C mode select bit 2 Clock-synchronous bit SCL wait output bit SDA output stop bit UARTi initialization bit SCL wait output bit 2 SDA output disable bit Refer to Table 1.16.4 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0: Transfer clock 1: 0 output
Function
RW RW RW RW RW RW RW RW
0: Enabled 1: Disabled (high impedance)
(b7)
Nothing is assigned. When write, set "0". When read, its content is indeterminate.
UARTi special mode register 3 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0SMR3 to U2SMR3 Bit symbol (b0) CKPH
Address 036D16, 037116, 037516
After reset 000X0X0X2
Bit name
Function
RW
Nothing is assigned. When write, set "0". When read, its content is indeterminate. Clock phase set bit 0 : Without clock delay 1 : With clock delay RW
(b2) NODC
Nothing is assigned. When write, set "0". When read, its content is indeterminate. Clock output select bit 0 : CLKi is CMOS output 1 : CLKi is N-channel open drain output RW
(b4) DL0
Nothing is assigned. When write, set "0". When read, its content is indeterminate. SDAi digital delay setup bit (Note 1, Note 2)
b7 b6 b5
DL1
DL2
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 : Without delay 1 : 1 to 2 cycle(s) of UiBRG count source 0 : 2 to 3 cycles of UiBRG count source 1 : 3 to 4 cycles of UiBRG count source 0 : 4 to 5 cycles of UiBRG count source 1 : 5 to 6 cycles of UiBRG count source 0 : 6 to 7 cycles of UiBRG count source 1 : 7 to 8 cycles of UiBRG count source
RW
RW
RW
Note 1 : The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I 2C mode. In other than I 2C mode, set these bits to "0002" (no delay). Note 2 : The amount of delay varies with the load on SCLi and SDAi pins. Also, when using an external clock, the amount of delay increases by about 100 ns.
Figure 1.13.7. U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 99 of 190
M16C/6S Group
Serial I/O
UARTi special mode register 4 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address U0SMR4 to U2SMR4 036C16, 037016, 037416 Bit symbol STAREQ
After reset 0016
Bit name Start condition generate bit (Note) 0 : Clear 1 : Start 0 : Clear 1 : Start 0 : Clear 1 : Start
Function
RW RW RW RW RW RW RW RW RW
RSTAREQ Restart condition generate bit (Note) STPREQ STSPSEL ACKD ACKC SCLHI SWC9 Stop condition generate bit (Note) SCL,SDA output select bit ACK data bit ACK data output enable bit SCL output stop enable bit SCL wait bit 3
0 : Start and stop conditions not output 1 : Start and stop conditions output 0 : ACK 1 : NACK 0 : Serial I/O data output 1 : ACK data output 0 : Disabled 1 : Enabled 0 : SCL "L" hold disabled 1 : SCL "L" hold enabled
Note: Set to "0" when each condition is generated.
Figure 1.13.8. U0SMR4 to U2SMR4 Registers
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M16C/6S Group
Clock Synchronous serial I/O Mode
Clock Synchronous serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.14.1 lists the specifications of the clock synchronous serial I/O mode. Table 1.14.2 lists the registers used in clock synchronous serial I/O mode and the register values set. UART2 is not available in this mode. Table 1.14.1. Clock Synchronous Serial I/O Mode Specifications
Item Transfer data format Transfer clock Specification * Transfer data length: 8 bits * UiMR(i=0 to 1) register's CKDIR bit = "0" (internal clock) : fj/ 2(n+1) fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16 * CKDIR bit = "1" (external clock) : Input from CLKi pin _______ _______ _______ _______ * Selectable from CTS function, RTS function or CTS/RTS function disable * Before transmission can start, the following requirements must be met (Note 1) _ The TE bit of UiC1 register= 1 (transmission enabled) _ The TI bit of UiC1 register = 0 (data present in UiTB register)
_
_______ _______
Transmission, reception control Transmission start condition
If CTS function is selected, input on the CTSi pin = "L"
Reception start condition
Interrupt request generation timing
* Before reception can start, the following requirements must be met (Note 1) The RE bit of UiC1 register= 1 (reception enabled) _ The TE bit of UiC1 register= 1 (transmission enabled) _ The TI bit of UiC1 register= 0 (data present in the UiTB register) * For transmission, one of the following conditions can be selected _ The UiIRS bit (Note 3) = 0 (transmit buffer empty): when transferring data from the UiTB register to the UARTi transmit register (at start of transmission) _ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from the UARTi transmit register * For reception When transferring data from the UARTi receive register to the UiRB register (at
_
Error detection
Select function
completion of reception) * Overrun error (Note 2) This error occurs if the serial I/O started receiving the next data before reading the UiRB register and received the 7th bit of the next data * CLK polarity selection Transfer data input/output can be chosen to occur synchronously with the rising or the falling edge of the transfer clock * LSB first, MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected * Continuous receive mode selection Reception is enabled immediately by reading the UiRB register * Switching serial data logic This function reverses the logic value of the transmit/receive data * Transfer clock output from multiple pins selection (UART1) The output pin can be selected in a program from two UART1 transfer clock pins that have been set _______ _______ * Separate CTS/RTS pins (UART0)
_________ _________
CTS0 and RTS0 are input/output from separate pins Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register's CKPOL bit = "0" (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the UiC0 register's CKPOL bit = "1" (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change. Note 3: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1.
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M16C/6S Group
Clock Synchronous serial I/O Mode
Table 1. 14. 2. Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register UiTB(Note3) Bit 0 to 7 OER UiBRG 0 to 7 CKDIR IOPOL UiC0 CLK1 to CLK0 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI U2IRS (Note 1) U2RRM (Note 1) UiLCH UiERE UiSMR UiSMR2 UiSMR3 0 to 7 0 to 7 0 to 2 NODC 4 to 7 UiSMR4 UCON 0 to 7 U0IRS, U1IRS U0RRM, U1RRM CLKMD0 CLKMD1 RCSP 7 UiMR(Note3) SMD2 to SMD0 Function Set transmission data Reception data can be read Overrun error flag Set a transfer rate Set to "0012" Select the internal clock or external clock Set to "0" Select the count source for the UiBRG register
_______ _______
UiRB(Note3) 0 to 7
Select CTS or RTS to use Transmit register empty flag
_______ _______
Enable or disable the CTS or RTS function Select TxDi pin output mode Select the transfer clock polarity Select the LSB first or MSB first Set this bit to "1" to enable transmission/reception Transmit buffer empty flag Set this bit to "1" to enable reception Reception complete flag Select the source of UART2 transmit interrupt Set this bit to "1" to use continuous receive mode Set this bit to "1" to use inverted data logic Set to "0" Set to "0" Set to "0" Set to "0" Select clock output mode Set to "0" Set to "0" Select the source of UART0/UART1 transmit interrupt Set this bit to "1" to use continuous receive mode Select the transfer clock output pin when CLKMD1 = 1 Set this bit to "1" to output UART1 transfer clock from two pins
_________
Set this bit to "1" to accept as input the UART0 CTS0 signal from the P64 pin Set to "0"
Note 1: Set the U0C1 and U1C1 register bit 4 and bit 5 to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits are in the UCON register. Note 2: Not all register bits are described above. Set those bits to "0" when writing to the registers in clock synchronous serial I/O mode. i=0 to 1
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M16C/6S Group
Clock Synchronous serial I/O Mode
Table 1.14.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 1.14.3 shows pin functions for the case where the multiple transfer clock output pin select function is deselected. Table 1.14.4 lists the P64 pin functions during clock synchronous serial I/O mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an "H". (If the N-channel open-drain output is selected, this pin is in a high-impedance state.) Table 1.14.3. Pin Functions (When Not Select Multiple Transfer Clock Output Pin Function)
Pin name Function Method of selection (Outputs dummy data when performing reception only) PD6 register's PD6_2 bit=0, PD6_6 bit=0 (Can be used as an input port when performing transmission only) UiMR register's CKDIR bit=0 UiMR register's CKDIR bit=1 PD6 register's PD6_1 bit=0, PD6_5 bit=0 UiC0 register's CRD bit=0 UiC0 register's CRS bit=0 PD6 register's PD6_0 bit=0, PD6_4 bit=0 UiC0 register's CRD bit=0 UiC0 register's CRS bit=1 UiC0 register's CRD bit=1 TxDi (i = 0 to 2) Serial data output (P63, P67) RxDi (P62, P66) CLKi (P61, P65) Serial data input Transfer clock output Transfer clock input CTSi/RTSi (P60, P64) CTS input
RTS output I/O port
Table 1.14.4. P64 Pin Functions
Pin function U1C0 register CRS CRD 1 0 0 1 0 0 0
Bit set value RCSP 0 0 0 1 UCON register CLKMD1 CLKMD0 0 0 0 0 1(Note 2) 1 PD6 register PD6_4 Input: 0, Output: 1 0 0
P64 CTS1 RTS1 CTS0(Note1) CLKS1
Note 1: In addition to this, set the U0C0 register's CRD bit to "0" (CTS0/RTS0 enabled) and the U0 C0 register's CRS bit to "1" (RTS0 selected). Note 2: When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output: * High if the U1C0 register's CLKPOL bit = 0 * Low if the U1C0 register's CLKPOL bit = 1
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Clock Synchronous serial I/O Mode
(1) Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
"1" "0" "1" "0" Transferred from UiTB register to UARTi transmit register "H" Write data to the UiTB register
UiC1 register TE bit UiC1 register TI bit CTSi
"L"
TCLK
Stopped pulsing because CTSi = "H"
Stopped pulsing because the TE bit = "0"
CLKi
TxDi UiC0 register TXEPT bit SiTIC register IR bit
"1" "0" "1" "0"
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Cleared to "0" when interrupt request is accepted, or cleared to "0" in a program Tc = TCLK = 2(n + 1) / fj fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) n: value set to UiBRG register i: 0 to 2 The above timing diagram applies to the case where the register bits are set as follows: * UiMR register CKDIR bit = 0 (internal clock) * UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected) * UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) * UiRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON register bit 1, and U2IRS bit is the U2C1 register bit 4
(2) Example of receive timing (when external clock is selected)
UiC1 register RE bit UiC1 register TE bit UiC1 register TI bit RTSi
"1" "0" "1" "0" "1" "0" "H" "L"
Write dummy data to UiTB register
Transferred from UiTB register to UARTi transmit register
Even if the reception is completed, the RTS does not change. The RTS becomes "L" when the RI bit changes to "0" from "1".
1 / fEXT
CLKi
Receive data is taken in
RxDi UiC1 register RI bit SiTIC register IR bit
"1" "0" "1" "0"
D0 D1 D2 D3 D4 D5 D6 D7
Transferred from UARTi receive register to UiRB register
D0 D1 D2
D3 D4 D5
Read out from UiRB register
Cleared to "0" when interrupt request is accepted, or cleared to "0" in a program The above timing diagram applies to the case where the register bits are set Make sure the following conditions are met when input as follows: to the CLKi pin before receiving data is high: * UiMR register CKDIR bit = 1 (external clock) * UiC0 register TE bit = 1 (transmit enabled) * UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected) * UiC0 register RE bit = 1 (Receive enabled) * UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive * Write dummy data to the UiTB register data taken in at the rising edge of the transfer clock) fEXT: frequency of external clock
Figure 1.14.1. Transmit and Receive Operation Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 104 of 190
M16C/6S Group
Clock Synchronous serial I/O Mode
Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below. * Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 register to "0" (reception disabled) (2) Set the SMD2 to SMD0 bits in the UiMR register to "000b" (Serial I/O disabled) (3) Set the SMD2 to SMD0 bits in the UiMR register to "001b" (Clock synchronous serial I/O mode) (4) Set the RE bit in the UiC1 register to "1" (reception enabled) * Resetting the UiTB register (i=0 to 2) (1) Set the SMD2 to SMD0 bits in the UiMR register "000b" (Serial I/O disabled) (2) Set the SMD2 to SMD0 bits in the UiMR register "001b" (Clock synchronous serial I/O mode) (3) "1" is written to RE bit in the UiC1 register (reception enabled), regardless of the TE bit in the UiCi register (a) CLK Polarity Select Function Use the UiC0 register (i = 0 to 1)'s CKPOL bit to select the transfer clock polarity. Figure 1.14.2 shows the polarity of the transfer clock.
(1) When the UiC0 register's CKPOL bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock)
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
(Note 2)
(2) When the UiC0 register's CKPOL bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock)
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
(Note 3)
Note 1: This applies to the case where the UiC0 register's UFORM bit = 0 (LSB first) and UiC1 register's UiLCH bit = 0 (no reverse). Note 2: When not transferring, the CLKi pin outputs a high signal. Note 3: When not transferring, the CLKi pin outputs a low signal. i = 0 to 1
Figure 1.14.2. Transfer Clock Polarity
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M16C/6S Group
Clock Synchronous serial I/O Mode
(b) LSB First/MSB First Select Function Use the UiC0 register (i = 0 to 1)'s UFORM bit to select the transfer format. Figure 1.14.3 shows the transfer format.
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLKi TXDi RXDi D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
Note: This applies to the case where the UiC0 register's CKPOL bit = 0 ( transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the UiC1 register's UiLCH bit = 0 (no reverse). i = 0 to 1
Figure 1.14.3. Transfer Format (c) Continuous Receive Mode In continuous receive mode, receive operation becomes enable when the receive buffer register is read. It is not necessary to write dummy data into the transmit buffer register to enable receive operation in this mode. However, a dummy read of the receive buffer register is required when starting the operation mode. When the UiRRM bit (i = 0 to 1) = 1 (continuous receive mode), the UiC1 register's TI bit is set to "1" (data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the UCON register bit 2 and bit 3, respectively. (d) Serial Data Logic Switching Function When the UiC1 register (i = 0 to 1)'s UiLCH bit = 1 (reverse), the data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register. Figure 1.14.4 shows serial data logic.
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Clock Synchronous serial I/O Mode
(1) When the UiC1 register's UiLCH bit = 0 (no reverse)
Transfer clock TxDi
(no reverse)
"H" "L" "H" "L"
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UiC1 register's UiLCH bit = 1 (reverse)
Transfer clock TxDi
(reverse)
"H" "L" "H" "L"
D0
D1
D2
D3
D4
D5
D6
D7
Note: This applies to the case where the UiC0 register's CKPOL bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the UFORM bit = 0 (LSB first). i = 0 to 1
Figure 1.14.4. Serial Data Logic Switching
(e) Transfer Clock Output From Multiple Pins (UART1) Use the UCON register's CLKMD1 to CLKMD0 bits to select one of the two transfer clock output pins. (See Figure 1.14.5.) This function can be used when the selected transfer clock for UART1 is an internal clock.
Microcomputer
TXD1 (P67)
CLKS1 (P64) CLK1 (P65) IN CLK IN CLK
Transfer enabled when the UCON register's CLKMD0 bit = 0
Transfer enabled when the UCON register's CLKMD0 bit = 1
Note: This applies to the case where the U1MRregister's CKDIR bit = 0 (internal clock) and the UCON register's CLKMD1 bit = 1 ( transfer clock output from multiple pins).
Figure 1.14.5. Transfer Clock Output From Multiple Pins
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_______ _______
CTS/RTS Function _______ ________ When the CTS function is used transmit and receive operation start when "L" is applied to the CTSi/ ________ ________ ________ RTSi (i=0 to 2) pin. Transmit and receive operation begins when the CTSi/RTSi pin is held "L". If the "L" signal is switched to "H" during a transmit or receive operation, the operation stops before the next data. _______ ________ ________ When the RTS function is used, the CTSi/RTSi pin outputs on "L" signal when the microcomputer is ready to receive. The output level becomes "H" on the first falling edge of the CLKi pin. _______ _______ * CRD bit in UiC0 register = 1 ( CTS/RTS function disabled) ________ ________ CTSi/RTSi pin is programmable I/O function _______ ________ ________ _______ * CRD bit = 0, CRS bit = 0 (CTS function is selected) CTSi/RTSi pin is CTS function _______ ________ ________ _______ * CRD bit = 0, CRS bit = 1 (RTS function is selected) CTSi/RTSi pin is RTS function
_______ _______
(f) CTS/RTS Separate Function (UART0) _______ _______ _______ _______ This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0 from the P64 pin. To use this function, set the register bits as shown below. _______ _______ * U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS) _______ * U0C0 register's CRS bit = 1 (outputs UART0 RTS) _______ _______ * U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS) _______ * U1C0 register's CRS bit = 0 (inputs UART1 CTS) _______ * UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin) * UCON register's CLKMD1 bit = 0 (CLKS1 not used) _______ _______ _______ _______ Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be used.
Microcomputer
TXD0 (P63) RXD0 (P62) CLK0 (P61) IN OUT CLK CTS RTS
IC
RTS0 (P60) CTS0 (P64)
_______ _______
Figure 1.14.6. CTS/RTS Separate Function
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M16C/6S Group
UART Mode
Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 1.15.1 lists the specifications of the UART mode. Table 1.15.1. UART Mode Specifications
Item Transfer data format Specification * Character bit (transfer data): Selectable from 7, 8 or 9 bits * Start bit: 1 bit * Parity bit: Selectable from odd, even, or none * Stop bit: Selectable from 1 or 2 bits * UiMR(i=0 to 2) register's CKDIR bit = 0 (internal clock) : fj/ 16(n+1) 0016 to FF16 fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register * CKDIR bit = "1" (external clock) : fEXT/16(n+1) (Note 3) fEXT: Input from CLKi pin. n :Setting value of UiBRG register 0016 to FF16 _______ _______ _______ _______ * Selectable from CTS function, RTS function or CTS/RTS function disable * Before transmission can start, the following requirements must be met _ The TE bit of UiC1 register= 1 (transmission enabled) _ The TI bit of UiC1 register = 0 (data present in UiTB register) _______ _______ _ If CTS function is selected, input on the CTSi pin = "L" * Before reception can start, the following requirements must be met _ The RE bit of UiC1 register= 1 (reception enabled) _ Start bit detection * For transmission, one of the following conditions can be selected _ The UiIRS bit (Note 2) = 0 (transmit buffer empty): when transferring data from the UiTB register to the UARTi transmit register (at start of transmission) _ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from the UARTi transmit register * For reception When transferring data from the UARTi receive register to the UiRB register (at completion of reception) * Overrun error (Note 1) This error occurs if the serial I/O started receiving the next data before reading the UiRB register and received the bit one before the last stop bit of the next data * Framing error This error occurs when the number of stop bits set is not detected * Parity error This error occurs when if parity is enabled, the number of 1's in parity and character bits does not match the number of 1's set * Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Transfer clock
Transmission, reception control Transmission start condition
Reception start condition
Interrupt request generation timing
Error detection
* LSB first, MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected * Serial data logic switch This function reverses the logic of the transmit/receive data. The start and stop bits are not reversed. * TXD, RXD I/O polarity switch This function reverses the polarities of hte TXD pin output and RXD pin input. The logic levels of all I/O data is reversed. _______ _______ * Separate CTS/RTS pins (UART0) _________ _________ CTS0 and RTS0 are input/output from separate pins Note 1: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change. Note 2: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4. Note 3: CKDIR of U2MR must be set "0" to select internal clock.
Select function
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UART Mode
Table 1. 15. 2. Registers to Be Used and Settings in UART Mode
Register UiTB UiRB UiBRG UiMR Bit 0 to 8 0 to 8 0 to 7 SMD2 to SMD0 Function Set transmission data (Note 1) Reception data can be read (Note 1) Set a transfer rate Set these bits to `1002' when transfer data is 7 bits long Set these bits to `1012' when transfer data is 8 bits long Set these bits to `1102' when transfer data is 9 bits long CKDIR STPS PRY, PRYE IOPOL UiC0 CLK0, CLK1 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI U2IRS (Note 2) U2RRM (Note 2) UiLCH UiERE UiSMR UiSMR2 UiSMR3 UiSMR4 UCON 0 to 7 0 to 7 0 to 7 0 to 7 U0IRS, U1IRS U0RRM, U1RRM CLKMD0 CLKMD1 RCSP 7 Select the internal clock or external clock Select the stop bit Select whether parity is included and whether odd or even Select the TxD/RxD input/output polarity Select the count source for the UiBRG register
_______ _______
OER,FER,PER,SUM Error flag
Select CTS or RTS to use Transmit register empty flag
_______ _______
Enable or disable the CTS or RTS function Select TxDi pin output mode (Note 2) Set to "0" LSB first or MSB first can be selected when transfer data is 8 bits long. Set this bit to "0" when transfer data is 7 or 9 bits long. Set this bit to "1" to enable transmission Transmit buffer empty flag Set this bit to "1" to enable reception Reception complete flag Select the source of UART2 transmit interrupt Set to "0" Set this bit to "1" to use inverted data logic Set to "0" Set to "0" Set to "0" Set to "0" Set to "0" Select the source of UART0/UART1 transmit interrupt Set to "0" Invalid because CLKMD1 = 0 Set to "0"
_________
Set this bit to "1" to accept as input the UART0 CTS0 signal from the P64 pin Set to "0"
Note 1: The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long; bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long. Note 2: Set the U0C1 and U1C1 registers bit 4 to bit 5 to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits are included in the UCON register. Note 3: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to "0". i=0 to 2
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M16C/6S Group
UART Mode
Table 1.15.3 lists the functions of the input/output pins during UART mode. Table 1.15.4 lists the P64 pin functions during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an "H". (If the N-channel open-drain output is selected, this pin is in a high-impedance state.) Table 1.15.3. I/O Pin Functions
Pin name Function Method of selection (Outputs dummy data when performing reception only) PD6 register's PD6_2 bit=0, PD6_6 bit=0, PD7 register's PD7_1 bit=0 (Can be used as an input port when performing transmission only) UiMR register's CKDIR bit=0 UiMR register's CKDIR bit=1 PD6 register's PD6_1 bit=0, PD6_5 bit=0, PD7 register's PD7_2 bit=0 UiC0 register's CRD bit=0 UiC0 register's CRS bit=0 PD6 register's PD6_0 bit=0, PD6_4 bit=0, PD7 register's PD7_3 bit=0 UiC0 register's CRD bit=0 UiC0 register's CRS bit=1 UiC0 register's CRD bit=1 TxDi (i = 0 to 2) Serial data output (P63, P67, P70) Serial data input RxDi (P62, P66, P71) CLKi (P61, P65) Input/output port Transfer clock input CTSi/RTSi CTS input (P60, P64, P73) RTS output Input/output port
Table 1.15.4. P64 Pin Functions
Pin function U1C0 register CRS CRD P64 CTS1 RTS1 CTS0 (Note) 1 0 0 0 0 1 0 Bit set value UCON register RCSP CLKMD1 0 0 0 1 0 0 0 0 PD6 register PD6_4 Input: 0, Output: 1 0 0
Note: In addition to this, set the U0C0 register's CRD bit to "0" (CTS0/RTS0 enabled) and the U0C0 register's CRS bit to "1" (RTS0 selected).
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M16C/6S Group
UART Mode
(1) Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock UiC1 register TE bit UiC1 register TI bit
"1" "0" "1" "0"
The transfer clock stops momentarily as CTSi is "H" when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTSi changes to "L".
Write data to the UiTB register
Transferred from UiTB register to UARTi transmit register
"H"
CTSi
"L"
Start bit TxDi UiC0 register TXEPT bit SiTIC register IR bit
"1" "0" "1" "0"
Parity Stop bit bit
P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Stopped pulsing because the TE bit = "0"
ST D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7
Cleared to "0" when interrupt request is accepted, or cleared to "0" in a program The above timing diagram applies to the case where the register bits are set as follows: * UiMR register PRYE bit = 1 (parity enabled) * UiMR register STPS bit = 0 (1 stop bit) * UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected) * UiRS bit = 1 (an interrupt request occurs when transmit completed): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON register bit 1, and U2IRS bit is the U2C1 register bit 4 Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : frequency of UiBRG count source (external clock) n : value set to UiBRG i: 0 to 2
(2) Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock UiC1 register TE bit UiC1 register TI bit
"1" "0" "1" "0"
Write data to the UiTB register
Start bit TxDi UiC0 register TXEPT bit SiTIC register IR bit
"1" "0" "1" "0"
Stop Stop bit bit
Transferred from UiTB register to UARTi transmit register
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP
ST D0 D1
Cleared to "0" when interrupt request is accepted, or cleared to "0" in a program Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT The above timing diagram applies to the case where the register bits are set as follows: fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) * UiMR register PRYE bit = 0 (parity disabled) fEXT : frequency of UiBRG count source (external clock) * UiMR register STPS bit = 1 (2 stop bits) n : value set to UiBRG * UiC0 register CRD bit = 1 (CTS/RTS disabled) i: 0 to 2 * UiRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON register bit 1, and U2IRS bit is the U2C1 register bit 4
Figure 1.15.1. Transmit Operation
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M16C/6S Group
UART Mode
* Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG count source UiC1 register RE bit RxDi "1" "0" Start bit Sampled "L" Receive data taken in Transfer clock UiC1 register RI bit RTSi SiRIC register IR bit Reception triggered when transfer clock "1" is generated by falling edge of start bit "0" "H" "L" "1" "0" Cleared to "0" when interrupt request is accepted, or cleared to "0" in a program The above timing diagram applies to the case where the register bits are set as follows: * UiMR register PRYE bit = 0 (parity disabled) * UiMR register STPS bit = 0 (1 stop bit) * UiC0 register CRD bit = 0 (CTSi/RTSi enabled), CRS bit = 1 (RTSi selected) i = 0 to 2 Transferred from UARTi receive register to UiRB register
Stop bit
D0
D1
D7
Figure 1.15.2. Receive Operation
Bit Rates In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates. Table 1.15.5 lists example of bit rates and settings.
Table 1.15.5. Example of Bit Rates and Settings
Bit Rate (bps) 1200 2400 4800 9600 14400 19200 28800 31250 38400 51200 Count Source of BRG f8 f8 f8 f1 f1 f1 f1 f1 f1 f1 Peripheral Function Clock : 16MHz Set Value of BRG : n 103 (67h) 51 (33h) 25 (19h) 103 (67h) 68 (44h) 51 (33h) 34 (22h) 31 (1Fh) 25 (19h) 19 (13h) Actual Time (bps) 1202 2404 4808 9615 14493 19231 28571 31250 38462 50000 Peripheral Function Clock : 24MHz Set value of BRG : n 155 (96h) 77 (46h) 38 (26h) 155 (96h) 103 (67h) 77 (46h) 51 (33h) 47 (2Fh) 38 (26h) 28 (1Ch) Actual Time (bps) 1202 2404 4808 9615 14423 19231 28846 31250 38462 51724
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M16C/6S Group
UART Mode
Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in UART mode, follow the procedures below. * Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 register to "0" (reception disabled) (2) Set the RE bit in the UiC1 register to "1" (reception enabled) * Resetting the UiTB register (i=0 to 2) (1) Set the SMD2 to SMD0 bits in the UiMR register "000b" (Serial I/O disabled) (2) Set the SMD2 to SMD0 bits in the UiMR register "001b", "101b", "110b". (3) "1" is written to RE bit in the UiC1 register (reception enabled), regardless of the TE bit in the UiCi register
(a) LSB First/MSB First Select Function As shown in Figure 1.15.3, use the UiC0 register's UFORM bit to select the transfer format. This function is valid when transfer data is 8 bits long.
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLKi TXDi RXDi ST ST D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 P P SP SP
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLKi TXDi RXDi ST ST D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 P P SP SP
Note: This applies to the case where the UiC0 register's CKPOL bit = 0 ( transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the UiC1 register's UiLCH bit = 0 (no reverse), UiMR register's STPS bit = 0 (1 stop bit) and UiMR register's PRYE bit = 1 (parity enabled).
Figure 1.15.3. Transfer Format
ST : Start bit P : Parity bit SP : Stop bit i = 0 to 2
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M16C/6S Group
UART Mode
(b) Serial Data Logic Switching Function The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register. Figure 1.15.4 shows serial data logic.
(1) When the UiC1 register's UiLCH bit = 0 (no reverse)
Transfer clock TxDi
(no reverse)
"H" "L" "H" "L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When the UiC1 register's UiLCH bit = 1 (reverse)
Transfer clock TxDi
(reverse)
"H" "L" "H" "L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
Note: This applies to the case where the UiC0 register's CKPOL bit = 0 ( transmit data output at the falling edge of the transfer clock), the UiC0 register's UFORM bit = 0 (LSB first), the UiMR register's STPS bit = 0 (1 stop bit) and UiMR register's PRYE bit = 1 (parity enabled).
ST : Start bit P : Parity bit SP : Stop bit i = 0 to 2
Figure 1.15.4. Serial Data Logic Switching
(c) TxD and RxD I/O Polarity Inverse Function This function inverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all input/output data (including the start, stop and parity bits) are inversed. Figure 1.15.5 shows the TXD pin output and RXD pin input polarity inverse.
(1) When the UiMR register's IOPOL bit = 0 (no reverse)
Transfer clock TxDi RxDi
"H" "L" "H"
(no reverse) "L"
"H"
ST ST
D0 D0
D1 D1
D2 D2
D3 D3
D4 D4
D5 D5
D6 D6
D7 D7
P P
SP SP
(no reverse) "L"
(2) When the UiMR register's IOPOL bit = 1 (reverse)
Transfer clock TxDi
(reverse)
"H" "L" "H" "L" "H" "L"
ST ST
D0 D0
D1 D1
D2 D2
D3 D3
D4 D4
D5 D5
D6 D6
D7 D7
P P
SP SP ST : Start bit P : Parity bit SP : Stop bit i = 0 to 2
RxDi
(reverse)
Note: This applies to the case where the UiC0 register's UFORM bit = 0 (LSB first), the UiMR register's STPS bit = 0 (1 stop bit) and the UiMR register's PRYE bit = 1 (parity enabled).
Figure 1.15.5. TXD and RXD I/O Polarity Inverse Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 115 of 190
M16C/6S Group
_______ _______
CTS/RTS Function _______ ________ ________ When the CTS function is used transmit operation start when "L" is applied to the CTSi/RTSi (i=0 to 2) ________ ________ pin. Transmit operation begins when the CTSi/RTSi pin is held "L". If the "L" signal is switched to "H" during a transmit operation, the operation stops before the next data. _______ ________ ________ When the RTS function is used, the CTSi/RTSi pin outputs on "L" signal when the microcomputer is ready to receive. The output level becomes "H" on the first falling edge of the CLKi pin. _______ _______ * CRD bit in UiC0 register = 1 (disable CTS/RTS function of UART0) ________ ________ CTSi/RTSi pin is programmable I/O function _______ ________ ________ _______ * CRD bit = 0, CRS bit = 0 (CTS function is selected) CTSi/RTSi pin is CTS function _______ ________ ________ _______ * CRD bit = 0, CRS bit = 1 (RTS function is selected) CTSi/RTSi pin is RTS function
_______ _______
(d) CTS/RTS Separate Function (UART0) _______ _______ _______ _______ This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0 from the P64 pin. To use this function, set the register bits as shown below. _______ _______ * U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS) _______ * U0C0 register's CRS bit = 1 (outputs UART0 RTS) _______ _______ * U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS) _______ * U1C0 register's CRS bit = 0 (inputs UART1 CTS) _______ * UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin) * UCON register's CLKMD1 bit = 0 (CLKS1 not used) _______ _______ _______ _______ Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be used.
Microcomputer
TXD0 (P63) RXD0 (P62) IN OUT
IC
RTS0 (P60) CTS0 (P64)
CTS RTS
_______ _______
Figure 1.15.6. CTS/RTS Separate Function
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M16C/6S Group
Special Mode
Special Mode 1 (I2C mode)
I2C mode is provided for use as a simplified I2C interface compatible mode. Table 1.16.1 lists the specifications of the I2C mode. Table 1.16.2 lists the registers used in the I2C mode and the register values set. Figure 1.16.1 shows the block diagram for I2C mode. Figure 1.16.2 shows SCLi timing. As shown in Table 1.16.3, the microcomputer is placed in I2C mode by setting the SMD2 to SMD0 bits to `0102' and the IICM bit to "1". Because SDAi transmit output has a delay circuit attached, SDAi output does not change state until SCLi goes low and remains stably low. Table 1.16.1. I2C Mode Specifications
Item Transfer data format Transfer clock Specification * Transfer data length: 8 bits * During master UiMR(i=0 to 2) register's CKDIR bit = "0" (internal clock) : fj/ 2(n+1) fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16 * During slave CKDIR bit = "1" (external clock) : Input from CLKi pin Transmission start condition * Before transmission can start, the following requirements must be met (Note 1) _ The TE bit of UiC1 register= 1 (transmission enabled) _ The TI bit of UiC1 register = 0 (data present in UiTB register) Reception start condition * Before reception can start, the following requirements must be met (Note 1) _ The RE bit of UiC1 register= 1 (reception enabled) _ The TE bit of UiC1 register= 1 (transmission enabled) _ The TI bit of UiC1 register= 0 (data present in the UiTB register) Interrupt request When start or stop condition is detected, acknowledge undetected, and acknowledge generation timing detected Error detection * Overrun error (Note 2) This error occurs if the serial I/O started receiving the next data before reading the UiRB register and received the 8th bit of the next data Select function * Arbitration lost Timing at which the UiRB register's ABT bit is updated can be selected * SDAi digital delay No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable * Clock phase setting With or without clock delay selectable Note 1: When an external clock is selected, the conditions must be met while the external clock is in the high state. Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
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M16C/6S Group
Special Mode
SDAi Delay circuit
Start and stop condition generation block STPSEL=1 STPSEL=0 ACK=0 SDHI ACKD register
DQ T
SDASTSP SCLSTSP
IICM2=1
DMA0, DMA1 request (UART1: DMA0 only)
ACK=1
Transmission register UARTi ALS
IICM=1 and IICM2=0
UARTi transmit, NACK interrupt request
Arbitration
IICM2=1
Noise Filter
DMA0 (UART0, UART2)
Reception register UARTi
Start condition detection
IICM=1 and IICM2=0
S R Q
UARTi receive, ACK interrupt request, DMA1 request
Bus busy
NACK
Stop condition detection
DQ T DQ T
SCLi
Falling edge detection IICM=0 I/O port
Q R
STPSEL=0 IICM=1 UARTi Noise Filter
Port register (Note) Internal clock SWC2 External clock
R S
ACK
9th bit
STPSEL=1
CLK control UARTi 9th bit falling edge SWC
Start/stop condition detection interrupt request
This diagram applies to the case where the UiMR register's SMD2 to SMD0 bits = 0102 and the UiSMR register's IICM bit = 1. IICM : Bit in UiSMR register IICM2, SWC, ALS, SWC2, SDHI : Bit in UiSMR2 register STSPSEL, ACKD, ACKC : Bit in UiSMR4 register i=0 to 2 Note: When the IICM bit =1, the pins can be read even if the direction bit = 1 (output).
Figure 1.16.1. I2C Mode Block Diagram
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Table 1. 16. 2. Registers to Be Used and Settings in I2C Mode (1) (Continued)
Register UiTB3 UiRB3 Bit 0 to 7 0 to 7 8 ABT OER 0 to 7 SMD2 to SMD0 CKDIR IOPOL CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM TE TI RE RI U2IRS1 U2RRM1, UiLCH, UiERE IICM ABC Function Master Slave Set transmission data Set transmission data Reception data can be read Reception data can be read ACK or NACK is set in this bit ACK or NACK is set in this bit Arbitration lost detection flag Invalid Overrun error flag Overrun error flag Set a transfer rate Invalid Set to `0102' Set to `0102' Set to "0" Set to "1" Set to "0" Set to "0" Select the count source for the UiBRG Invalid register Invalid because CRD = 1 Invalid because CRD = 1 Transmit buffer empty flag Transmit buffer empty flag Set to "1" Set to "1" Set to "1"2 Set to "1"2 Set to "0" Set to "0" Set to "1" Set to "1" Set this bit to "1" to enable transmission Set this bit to "1" to enable transmission Transmit buffer empty flag Transmit buffer empty flag Set this bit to "1" to enable reception Set this bit to "1" to enable reception Reception complete flag Reception complete flag Invalid Invalid Set to "0" Set to "0" Set to "1" Select the timing at which arbitration-lost is detected Bus busy flag Set to "0" Refer to Table 1.16.4. Set this bit to "1" to enable clock synchronization Set this bit to "1" to have SCLi output fixed to "L" at the falling edge of the 9th bit of clock Set this bit to "1" to have SDAi output stopped when arbitration-lost is detected Set to "0" Set to "1" Invalid Bus busy flag Set to "0" Refer to Table 1.16.4. Set to "0" Set this bit to "1" to have SCLi output fixed to "L" at the falling edge of the 9th bit of clock Set to "0" Set this bit to "1" to initialize UARTi at start condition detection Set this bit to "1" to have SCLi output forcibly pulled low Set this bit to "1" to disable SDAi output Set to "0" Set to "0" Refer to Table 1.16.4 Set the amount of SDAi digital delay
UiBRG UiMR3
UiC0
UiC1
UiSMR
BBS 3 to 7 UiSMR2 IICM2 CSC SWC
ALS STAC SWC2
Set this bit to "1" to have SCLi output forcibly pulled low SDHI Set this bit to "1" to disable SDAi output 7 Set to "0" UiSMR3 0, 2, 4 and NODC Set to "0" CKPH Refer to Table 1.16.4 DL2 to DL0 Set the amount of SDAi digital delay
i=0 to 2 Notes: 1. Set the U0C1 and U1C1 register bit 4 and bit 5 to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits are in the UCON register. 2. TxD2 pin is N channel open-drain output. Set the NCH bit in the U2C0 register to "0". 3. Not all register bits are described above. Set those bits to "0" when writing to the registers in I2C mode. Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 119 of 190
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Table 1. 16. 3. Registers to Be Used and Settings in I2C Mode (2) (Continued)
Register Bit Function Master Slave Set this bit to "1" to generate start Set to "0" condition Set this bit to "1" to generate restart Set to "0" condition Set this bit to "1" to generate stop Set to "0" condition Set this bit to "1" to output each condition Set to "0" Select ACK or NACK Select ACK or NACK Set this bit to "1" to output ACK data Set this bit to "1" to output ACK data Set this bit to "1" to have SCLi output Set to "0" stopped when stop condition is detected Set to "0" Set this bit to "1" to set the SCLi to "L" hold at the falling edge of the 9th bit of clock Set to "1" Set to "1" Invalid Invalid Set to "0" Set to "0"
UiSMR4 STAREQ RSTAREQ STPREQ STSPSEL ACKD ACKC SCLHI SWC9
IFSR2A IFSR26, ISFR27 UCON U0IRS, U1IRS 2 to 7
i=0 to 2
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Table 1.16.4. I2C Mode Functions
Function Clock Synchronous Serial I/O I2C Mode (SMD2 to SMD0 = 010b, IICM = 1) Mode (SMD2 to SMD0 = 001b, IICM2 = 0 IICM2 = 1 IICM = 0) (NACK/ACK interrupt) (UART transmit/ receive interrupt) CKPH = 1 CKPH = 1 CKPH = 0 CKPH = 0 (Clock delay) (No clock delay) (Clock delay) (No clock delay) Start condition detection or stop condition detection (See Table 1.16.5 STSPSEL Bit Function s) No acknowledgment detection (NACK) Rising edge of SCLi 9th bit Acknowledgment detection (ACK) Rising edge of SCLi 9th bit Rising edge of SCLi 9th bit UARTi transmission UARTi transmission Falling edge of SCLi Rising edge of next to the 9th bit SCLi 9th bit UARTi reception Falling edge of SCLi 9th bit
Factor of Interrupt Number 6, 7 and 10 (1, 5, 7) Factor of Interrupt Number UARTi transmission 15, 17 and 19 (1, 6) Transmission started or completed (selected by UiIRS) Factor of Interrupt Number UARTi reception When 8th bit received 16, 18 and 20 (1, 6) CKPOL = 0 (rising edge) CKPOL = 1 (falling edge) Timing for Transferring CKPOL = 0 (rising edge) Data From the UART CKPOL = 1 (falling edge) Reception Shift Register to the UiRB Register UARTi Transmission Not delayed Output Delay Functions of P6_3, P6_7 and P7_0 Pins Functions of P6_2, P6_6 and P7_1 Pins Functions of P6_1, P6_5 and P7_2 Pins Noise Filter Width Read RXDi and SCLi Pin Levels Initial Value of TXDi and SDAi Outputs Initial and End Values of SCLi DMA1 Factor (6) UARTi reception 1st to 8th bits of the received data are stored into bits 7 to 0 in the UiRB register TXDi output RXDi input CLKi input or output selected 15ns
Falling edge of SCLi 9th bit
Falling and rising edges of SCLi 9th bit
Delayed SDAi input/output SCLi input/output (Cannot be used in I2C mode) 200ns
Always possible no matter how the corresponding port direction bit is set Possible when the corresponding port direction bit =0 CKPOL = 0 (H) The value set in the port register before setting I2C mode (2) CKPOL = 1 (L) H L H L
Acknowledgment detection (ACK)
UARTi reception Falling edge of SCLi 9th bit
Store Received Data
1st to 8th bits of the received 1st to 7th bits of the received data are data are stored into bits 7 to 0 stored into bits 6 to 0 in the UiRB register. 8th bit is stored into bit 8 in the in the UiRB register UiRB register. 1st to 8th bits are stored into bits 7 to 0 in the UiRB register (3) Bits 6 to 0 in the UiRB register (4) are read as bits 7 to 1. Bit 8 in the UiRB register is read as bit 0.
Read Received Data
The UiRB register status is read
i = 0 to 2
NOTES : 1. If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to "1" (interrupt requested). (Refer to 24.6 Precautions for Interrupts) If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to clear the IR bit to "0" (interrupt not requested) after changing those bits. SMD2 to SMD0 bits in the UiMR register, IICM bit in the UiSMR register, IICM2 bit in the UiSMR2 register, CKPH bit in the UiSMR3 register 2. Set the initial value of SDAi output while the SMD2 to SMD0 bits in the UiMR register = 000b (serial I/O disabled). 3. Second data transfer to UiRB register (Rising edge of SCLi 9th bit) 4. First data transfer to UiRB register (Falling edge of SCLi 9th bit) 5. See Figure 1.16.4 STSPSEL Bit Function s. 6. See Figure 1.16.2 Transfer to UiRB Register and Interrupt Timing . 7. When using UART0, be sure to set the IFSR26 bit in the IFSR2A register to "1" (factor of interrupt: UART0 bus collision). When using UART1, be sure to set the IFSR27 bit to "1" (factor of interrupt: UART1 bus collision).
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Special Mode
(1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay)
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)
ACK interrupt (DMA1 request), NACK interrupt Transfer to UiRB register
b15 *** b9 b8 D8 b7 D7 D6 D5 D4 D3 D2 D1 b0 D0
UiRB register
(2) IICM2= 0, CKPH= 1 (clock delay)
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)
ACK interrupt (DMA1 request), NACK interrupt Transfer to UiRB register
b15 *** b9 b8 D8 b7 D7 D6 D5 D4 D3 D2 D1 b0 D0
UiRB register
(3) IICM2= 1 (UART transmit/receive interrupt), CKPH= 0
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)
Transmit interrupt
Receive interrupt (DMA1 request)
Transfer to UiRB register
b15 *** b9 b8 D0 b7 D7 D6 D5 D4 D3 D2 b0 D1
UiRB register
(4) IICM2= 1, CKPH= 1
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK, NACK)
Transmit interrupt
Receive interrupt (DMA1 request)
Transfer to UiRB register
b15 *** b9 b8 D0 b7 D7 D6 D5 D4 D3 D2 b0 D1
Transfer to UiRB register
b15 *** b9 b8 D8 b7 D7 D6 D5 D4 D3 D2 D1 b0 D0
i=0 to 2
UiRB register
UiRB register
This diagram applies to the case where the following condition is met. * UiMR register CKDIR bit = 0 (Slave selected)
Figure 1.16.2. Transfer to UiRB Register and Interrupt Timing Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 122 of 190
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Special Mode
* Detection of Start and Stop Condtion Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDAi pin changes state from high to low while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated when the SDAi pin changes state from low to high while the SCLi pin is in the high state. Because the start and stop condition-detected interrupts share the interrupt control register and vector, check the UiSMR register's BBS bit to determine which interrupt source is requesting the interrupt.
3 to 6 cycles < duration for setting-up (Note) 3 to 6 cycles < duration for holding (Note) Duration for setting up
SCLi SDAi
Duration for holding
(Start condition)
SDA i
(Stop condition)
i = 0 to 2 Note: When the PCLKR register's PCLK1 bit = 1, this is the cycle number of f1SIO, and the PCLK1 bit = 0, this is the cycle number of f2SIO.
Figure 1.16.3. Detection of Start and Stop Condition
* Output of Start and Stop Condition A start condition is generated by setting the STAREQ bit in the UiSMR4 register (i = 0 to 2) to "1" (start). A restart condition is generated by setting the RSTAREQ bit in the UiSMR4 register to "1" (start). A stop condition is generated by setting the STPREQ bit in the UiSMR4 register to "1" (start). The output procedure is described below. (1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to "1" (start). (2) Set the STSPSEL bit in the UiSMR4 register to "1" (output). The function of the STSPSEL bit is shown in Table 1.16.5 and Figure 1.16.4.
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Table 1.16.5. STSPSEL Bit Functions Function Output of SCLi and SDAi pins STSPSEL = 0 Output of transfer clock and data Output of start/stop condition is accomplished by a program using ports (not automatically generated in hardware) Start/stop condition detection STSPSEL = 1 Output of a start/stop condition according to the STAREQ, RSTAREQ and STPREQ bit
Star/stop condition interrupt request generation timing
Finish generating start/stop condition
(1) When slave CKDIR=1 (external clock) STPSEL bit 0
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SCLi SDAi Start condition detection interrupt
Stop condition detection interrupt
(2) When master CKDIR=0 (internal clock), CKPH=1 (clock delayed) STPSEL bit
Set to "1" in a program Set to "0" in a program Set to "1" in a program Set to "0" in a program
SCLi SDAi
Set STAREQ= 1 (start)
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
Start condition detection interrupt
Set STPREQ= 1 (start)
Stop condition detection interrupt
Figure 1.16.4. STSPSEL Bit Functions * Arbitration Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising edge of SCLi. Use the UiSMR register's ABC bit to select the timing at which the UiRB register's ABT bit is updated. If the ABC bit = 0 (updated bitwise), the ABT bit is set to "1" at the same time unmatching is detected during check, and is cleared to "0" when not detected. In cases when the ABC bit is set to "1", if unmatching is detected even once during check, the ABT bit is set to "1" (unmatching detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be updated bytewise, clear the ABT bit to "0" (undetected) after detecting acknowledge in the first byte, before transferring the next byte. Setting the UiSMR2 register's ALS bit to "1" (SDA output stop enabled) causes arbitration-lost to occur, in which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit is set to "1" (unmatching detected). Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 124 of 190
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* Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 1.16.4. The UiSMR2 register's CSC bit is used to synchronize the internally generated clock (internal SCLi) and an external clock supplied to the SCLi pin. In cases when the CSC bit is set to "1" (clock synchronization enabled), if a falling edge on the SCLi pin is detected while the internal SCLi is high, the internal SCLi goes low, at which time the UiBRG register value is reloaded with and starts counting in the low-level interval. If the internal SCLi changes state from low to high while the SCLi pin is low, counting stops, and when the SCLi pin goes high, counting restarts. In this way, the UARTi transfer clock is comprised of the logical product of the internal SCLi and SCLi pin signal. The transfer clock works from a half period before the falling edge of the internal SCLi 1st bit to the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock. The UiSMR2 register's SWC bit allows to select whether the SCLi pin should be fixed to or freed from low-level output at the falling edge of the 9th clock pulse. If the UiSMR4 register's SCLHI bit is set to "1" (enabled), SCLi output is turned off (placed in the highimpedance state) when a stop condition is detected. Setting the UiSMR2 register's SWC2 bit = 1 (0 output) makes it possible to forcibly output a low-level signal from the SCLi pin even while sending or receiving data. Clearing the SWC2 bit to "0" (transfer clock) allows the transfer clock to be output from or supplied to the SCLi pin, instead of outputting a low-level signal. If the UiSMR4 register's SWC9 bit is set to "1" (SCL hold low enabled) when the UiSMR3 register's CKPH bit = 1, the SCLi pin is fixed to low-level output at the falling edge of the clock pulse next to the ninth. Setting the SWC9 bit = 0 (SCL hold low disabled) frees the SCLi pin from low-level output. * SDA Output The data written to the UiTB register bit 7 to bit 0 (D7 to D0) is sequentially output beginning with D7. The ninth bit (D8) is ACK or NACK. The initial value of SDAi transmit output can only be set when IICM = 1 (I2C mode) and the UiMR register's SMD2 to SMD0 bits = `0002' (serial I/O disabled). The UiSMR3 register's DL2 to DL0 bits allow to add no delays or a delay of 2 to 8 UiBRG count source clock cycles to SDAi output. Setting the UiSMR2 register's SDHI bit = 1 (SDA output disabled) forcibly places the SDAi pin in the high-impedance state. Do not write to the SDHI bit synchronously with the rising edge of the UARTi transfer clock. This is because the ABT bit may inadvertently be set to "1" (detected). * SDA Input When the IICM2 bit = 0, the 1st to 8th bits (D7 to D0) of received data are stored in the UiRB register bit 7 to bit 0. The 9th bit (D8) is ACK or NACK. When the IICM2 bit = 1, the 1st to 7th bits (D7 to D1) of received data are stored in the UiRB register bit 6 to bit 0 and the 8th bit (D0) is stored in the UiRB register bit 8. Even when the IICM2 bit = 1, providing the CKPH bit = 1, the same data as when the IICM2 bit = 0 can be read out by reading the UiRB register after the rising edge of the corresponding clock pulse of 9th bit.
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Special Mode
* ACK and NACK If the STSPSEL bit in the UiSMR4 register is set to "0" (start and stop conditions not generated) and the ACKC bit in the UiSMR4 register is se to "1" (ACK data output), the value of the ACKD bit in the UiSMR4 register is output from the SDAi pin. If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDAi pin is low at the rising edge of the 9th bit of transmit clock pulse. If ACKi is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an acknowledge. * Initialization of Transmission/Reception If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial I/O operates as described below. - The transmit shift register is initialized, and the content of the UiTB register is transferred to the transmit shift register. In this way, the serial I/O starts sending data synchronously with the next clock pulse applied. However, the UARTi output value does not change state and remains the same as when a start condition was detected until the first bit of data is output synchronously with the input clock. - The receive shift register is initialized, and the serial I/O starts receiving data synchronously with the next clock pulse applied. - The SWC bit is set to "1" (SCL wait output enabled). Consequently, the SCLi pin is pulled low at the falling edge of the ninth clock pulse. Note that when UARTi transmission/reception is started using this function, the TI does not change state. Note also that when using this function, the selected transfer clock should be an external clock.
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Special Mode
Special Mode 2
Multiple slaves can be serially communicated from one master. Synchronous clock polarity and phase are selectable. Table 1.16.6 lists the specifications of Special Mode 2. Table 1.16.7 lists the registers used in Special Mode 2 and the register values set. Figure 1.16.5 shows communication control example for Special Mode 2. UART2 is not available in this mode.
Table 1.16.6. Special Mode 2 Specifications
Item Transfer data format Transfer clock Specification * Transfer data length: 8 bits * Master mode UiMR(i=0 to 1) register's CKDIR bit = "0" (internal clock) : fj/ 2(n+1) fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16 * Slave mode CKDIR bit = "1" (external clock selected) : Input from CLKi pin Transmit/receive control Controlled by input/output ports Transmission start condition * Before transmission can start, the following requirements must be met (Note 1) _ The TE bit of UiC1 register= 1 (transmission enabled) _ The TI bit of UiC1 register = 0 (data present in UiTB register) Reception start condition * Before reception can start, the following requirements must be met (Note 1) _ The RE bit of UiC1 register= 1 (reception enabled) _ The TE bit of UiC1 register= 1 (transmission enabled) _ The TI bit of UiC1 register= 0 (data present in the UiTB register) Interrupt request * For transmission, one of the following conditions can be selected _ The UiIRS bit of UiC1 register = 0 (transmit buffer empty): when transferring data generation timing from the UiTB register to the UARTi transmit register (at start of transmission) _ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from the UARTi transmit register * For reception When transferring data from the UARTi receive register to the UiRB register (at completion of reception) Error detection * Overrun error (Note 2) This error occurs if the serial I/O started receiving the next data before reading the UiRB register and received the 7th bit of the next data Select function * Clock phase setting Selectable from four combinations of transfer clock polarities and phases Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register's CKPOL bit = "0" (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the UiC0 register's CKPOL bit = "1" (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
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Special Mode
P81 P80 P83 P61(CLK0) P62(RxD0) P63(TxD0) Microcomputer (Master) P61(CLK0) P62(RxD0) P63(TxD0) Microcomputer (Slave)
P93 P61(CLK0) P62(RxD0) P63(TxD0) Microcomputer (Slave)
Figure 1.16.5. Serial Bus Communication Control Example (UART0)
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Special Mode
Table 1. 16. 7. Registers to Be Used and Settings in Special Mode 2
Register Bit UiTB(Note2) 0 to 7 UiRB(Note2) 0 to 7 OER UiBRG 0 to 7 UiMR(Note2) SMD2 to SMD0 CKDIR IOPOL UiC0 CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI U2IRS (Note 1) U2RRM(Note 1), U2LCH, UiERE UiSMR 0 to 7 UiSMR2 0 to 7 UiSMR3 CKPH NODC 0, 2, 4 to 7 UiSMR4 0 to 7 UCON U0IRS, U1IRS U0RRM, U1RRM CLKMD0 CLKMD1, RCSP, 7 Function Set transmission data Reception data can be read Overrun error flag Set a transfer rate Set to `0012' Set this bit to "0" for master mode or "1" for slave mode Set to "0" Select the count source for the UiBRG register Invalid because CRD = 1 Transmit register empty flag Set to "1" Select TxDi pin output format Clock phases can be set in combination with the UiSMR3 register's CKPH bit Set to "0" Set this bit to "1" to enable transmission Transmit buffer empty flag Set this bit to "1" to enable reception Reception complete flag Select UART2 transmit interrupt cause Set to "0" Set to "0" Set to "0" Clock phases can be set in combination with the UiC0 register's CKPOL bit Set to "0" Set to "0" Set to "0" Select UART0 and UART1 transmit interrupt cause Set to "0" Invalid because CLKMD1 = 0 Set to "0"
Note 1: Set the U0C0 and U1C1 register bit 4 and bit 5 to "0". The U0IRS, U1IRS, U0RRM and U1RRM bits are in the UCON register. Note 2: Not all register bits are described above. Set those bits to "0" when writing to the registers in Special Mode 2. i = 0 to 1
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Special Mode
* Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the UiSMR3 register's CKPH bit and the UiC0 register's CKPOL bit. Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated. Figure 1.16.6 shows the transmission and reception timing in master (internal clock). Figure 1.16.7 shows the transmission and reception timing (CKPH=0) in slave (external clock) while Figure 1.16.8 shows the transmission and reception timing (CKPH=1) in slave (external clock).
"H" Clock output (CKPOL=0, CKPH=0) "L"
"H" Clock output (CKPOL=1, CKPH=0) "L"
Clock output "H" (CKPOL=0, CKPH=1) "L"
"H" Clock output (CKPOL=1, CKPH=1) "L"
Data output timing
"H" "L"
D0
D1
D2
D3
D4
D5
D6
D7
Data input timing
Figure 1.16.6. Transmission and Reception Timing in Master Mode (Internal Clock)
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Special Mode
"H"
Slave control input
"L"
"H" Clock input (CKPOL=0, CKPH=0) "L"
"H" Clock input (CKPOL=1, CKPH=0) "L"
Data output timing (Note) Data input timing
"H" "L"
D0
D1
D2
D3
D4
D5
D6
D7
Indeterminate
Figure 1.16.7. Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock)
"H"
Slave control input
"L"
"H" Clock input (CKPOL=0, CKPH=1) "L"
"H" Clock input (CKPOL=1, CKPH=1) "L"
Data output timing (Note) Data input timing
"H" "L"
D0
D1
D2
D3
D4
D5
D6
D7
Figure 1.16.8. Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock)
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SI/O3 and SI/O4
SI/O3 and SI/O4
SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os. Figure 1.17.1 shows the block diagram of SI/O3 and SI/O4, and Figure 1.17.2 shows the SI/O3 and SI/O4related registers. SI/O4 is derectly connected to IT800 internally. Table 1.17.1 shows the specifications of SI/O3 and SI/O4.
1/2 Main clock, or On-chip Oscillator clock f1SIO
f2SIO
PCLK1=0
Clock source select SMi1 to SMi0 002 f8SIO f32SIO 012 102
Synchronous circuit
Data bus
1/8
PCLK1=1 1/4
1/2
1/(n+1)
SiBRG register
SMi4 CLKi
CLK polarity reversing circuit
SMi3 SMi6
SMi6 SI/O counter i SI/Oi interrupt request
SMi2 SMi3 SOUTi SINi SMi5 LSB MSB
SiTRR register 8 Note: i = 3, 4. n = A value set in the SiBRG register.
Figure 1.17.1. SI/O3 and SI/O4 Block Diagram
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SI/O3 and SI/O4
S I/Oi control register (i = 3, 4) (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol S3C S4C Bit symbol
SMi0 SMi1 SMi2 SMi3 SMi4
Address 036216 036616 Bit name
After reset 010000016 010000016 Description
b1 b0
RW RW RW RW RW
Internal synchronous clock select bit
0 0 : Selecting f1SIO or f2SIO 0 1 : Selecting f8SIO 1 0 : Selecting f32SIO 1 1 : Must not be set. 0 : SOUTi output 1 : SOUTi output disable(high impedance)
SOUTi output disable bit (Note 4) S I/Oi port select bit CLK polarity select bit
0 : Input/output port 1 : SOUTi output, CLKi function
0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge
RW
SMi5 SMi6 SMi7
Transfer direction select bit Synchronous clock select bit SOUTi initial value set bit
0 : LSB first 1 : MSB first 0 : External clock (Note 2) 1 : Internal clock (Note 3) Effective when SMi3 = 0 0 : "L" output 1 : "H" output
RW RW RW
Note 1: Make sure this register is written to by the next instruction after setting the PRCR register's PRC2 bit to "1" (write enable). Note 2: Set the SMi3 bit to "1" (SOUTi output, CLKi function). Note 3: Set the SMi3 bit to "1" and the corresponding port direction bit to "0" (input mode). Note 4: Effective when SMi3 bit = 1.
SI/Oi bit rate generator (i = 3, 4) (Notes 1, 2)
b7 b0
Symbol S3BRG S4BRG Description
Address 036316 036716
After reset Indeterminate Indeterminate
Setting range 0016 to FF16 RW WO
Assuming that set value = n, BRGi divides the count source by n + 1 Note 1: Write to this register while serial I/O is neither transmitting nor receiving. Note 2: Use MOV instruction to write to this register.
SI/Oi transmit/receive register (i = 3, 4) (Note 1, 2)
b7 b0
Symbol S3TRR S4TRR
Address 036016 036416 Description
After reset Indeterminate Indeterminate
RW RW
Transmission/reception starts by writing transmit data to this register. After transmission/reception finishes, reception data can be read by reading this register. Note 1: Write to this register while serial I/O is neither transmitting nor receiving. Note 2: To receive data, set the corresponding port direction bit for SINi to "0" (input mode).
Figure 1.17.2. S3C and S4C Registers, S3BRG and S4BRG Registers, and S3TRR and S4TRR Registers Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 133 of 190
M16C/6S Group
SI/O3 and SI/O4
Table 1.17.1. SI/O3 and SI/O4 Specifications
Item Transfer data format Transfer clock Specification * Transfer data length: 8 bits * SiC (i=3, 4) register's SMi6 bit = "1" (internal clock) : fj/ 2(n+1) fj = f1SIO, f8SIO, f32SIO. n=Setting value of SiBRG register 0016 to FF16. * SMi6 bit = "0" (external clock) : Input from CLKi pin (Note 1) * Before transmission/reception can start, the following requirements must be met Write transmit data to the SiTRR register (Notes 2, 3) * When SiC register's SMi4 bit = 0 The rising edge of the last transfer clock pulse (Note 4) * When SMi4 = 1 The falling edge of the last transfer clock pulse (Note 4) I/O port, transfer clock input, transfer clock output I/O port, transmit data output, high-impedance I/O port, receive data input * LSB first or MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected * Function for setting an SOUTi initial value set function When the SiC register's SMi6 bit = 0 (external clock), the SOUTi pin output level while not tranmitting can be selected. * CLK polarity selection Whether transmit data is output/input timing at the rising edge or falling edge of transfer clock can be selected. Note 1: To set the SiC register's SMi6 bit to "0" (external clock), follow the procedure described below. * If the SiC register's SMi4 bit = 0, write transmit data to the SiTRR register while input on the CLKi pin is high. The same applies when rewriting the SiC register's SMi7 bit. * If the SMi4 bit = 1, write transmit data to the SiTRR register while input on the CLKi pin is low. The same applies when rewriting the SMi7 bit. * Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop the transfer clock after supplying eight pulses. If the SMi6 bit = 1 (internal clock), the transfer clock automatically stops. Note 2: Unlike UART0 to UART2, SI/Oi (i = 3 to 4) is not separated between the transfer register and buffer. Therefore, do not write the next transmit data to the SiTRR register during transmission. Note 3: When the SiC register's SMi6 bit = 1 (internal clock), SOUTi retains the last data for a 1/2 transfer clock period after completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is written to the SiTRR register during this period, SOUTi immediately goes to a high-impedance state, with the data hold time thereby reduced. Note 4: When the SiC register's SMi6 bit = 1 (internal clock), the transfer clock stops in the high state if the SMi4 bit = 0, or stops in the low state if the SMi4 bit = 1. CLKi pin fucntion SOUTi pin function SINi pin function Select function
Transmission/reception start condition Interrupt request generation timing
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M16C/6S Group
SI/O3 and SI/O4
(a) SI/Oi Operation Timing Figure 1.17.3 shows the SI/Oi operation timing
1.5 cycle (max) (Note 3) SI/Oi internal clock CLKi output Signal written to the SiTRR register SOUTi output SINi input
"H" "L" "H" "L" "H" "L"
(Note 2)
"H" "L" "H" "L"
D0
D1
D2
D3
D4
D5
D6
D7
SiIC register IR bit
i= 3, 4
"1" "0"
Note 1: This diagram applies to the case where the SiC register bits are set as follows: SMi2=0 (SOUTi output), SMi3=1 (SOUTi output, CLKi function), SMi4=0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock), SMi5=0 (LSB first) and SMi6=1 (internal clock) Note 2: When the SMi6 bit = 1 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer finishes. Note 3: If the SMi6 bit=0 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the SiTRR register.
Figure 1.17.3. SI/Oi Operation Timing
(b) CLK Polarity Selection The SiC register's SMi4 bit allows selection of the polarity of the transfer clock. Figure 1.17.4 shows the polarity of the transfer clock.
(1) When SiC register's SMi4 bit = "0"
CLKi SINi SOUTi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
(Note 2)
(2) When SiC register's SMi4 bit = "1"
CLKi SINi SOUTi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
(Note 3)
i=3 and 4 Note 1: This diagram applies to the case where the SiC register bits are set as follows: SMi5=0 (LSB first) and SMi6=1 (internal clock) Note 2: When the SMi6 bit=1 (internal clock), a high level is output from the CLKi pin if not transferring data. Note 3: When the SMi6 bit=1 (internal clock), a low level is output from the CLKi pin if not transferring data.
Figure 1.17.4. Polarity of Transfer Clock Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 135 of 190
M16C/6S Group
SI/O3 and SI/O4
(c) Functions for Setting an SOUTi Initial Value If the SiC register's SMi6 bit = 0 (external clock), the SOUTi pin output can be fixed high or low when not transferring. Figure 1.17.5 shows the timing chart for setting an SOUTi initial value and how to set it.
(Example) When "H" selected for SOUTi initial value (Note 1)
Signal written to SiTRR register
Setting of the initial value of SOUTi output and starting of transmission/ reception
SMi7 bit
Set the SMi3 bit to "0" (SOUTi pin functions as an I/O port)
SMi3 bit
Set the SMi7 bit to "1" (SOUTi initial value = "H")
D0 SOUTi (internal)
Port output SOUTi pin output Initial value = "H" (Note 3) (i = 3, 4) Setting the SOUTi initial value to "H" (Note 2) Port selection switching (I/O port SOUTi)
D0
Set the SMi3 bit to "1" (SOUTi pin functions as SOUTi output) "H" level is output from the SOUTi pin Write to the SiTRR register
Note 1: This diagram applies to the case where the SiC register bits are set as follows: SMi2=0 (SOUTi output), SMi5=0 (LSB first) and SMi6=0 (external clock) Note 2: SOUTi can only be initialized when input on the CLKi pin is in the high state if the SiC register's SMi4 bit = 0 (transmit data output at the falling edge of the transfer clock) or in the low state if the SMi4 bit = 1 (transmit data output at the rising edge of the transfer clock). Note 3: If the SMi6 bit = 1 (internal clock) or if the SMi2 bit = 1 (SOUT output disabled), this output goes to the high-impedance state.
Serial transmit/reception starts
Figure 1.17.5. SOUTi's Initial Value Setting
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M16C/6S Group
Programmable I/O Ports
Programmable I/O Ports
The programmable input/output ports (hereafter referred to simply as "I/O ports") consist of 55 lines P1, P4 to P9 (except P85). Each port can be set for input or output every line by using a direction register, and can also be chosen to be or not be pulled high every 4 lines. P85 is an input-only port and does not have a pullup resistor. There is no external connections for port P1_0 to P1_4, P1_6 to P1_7, P4_0 to P4_7, P5_0 to P5_7, P7_2, P7_5, P7_7, P8_2, P8_6 to P8_7, P9_3 to P9_7. Figures 1.18.1 to 1.18.4 show the I/O ports. Figure 1.18.5 shows the I/O pins. Each pin functions as an I/O port, a peripheral function input/output. For details on how to set peripheral functions, refer to each functional description in this manual. If any pin is used as a peripheral function input, set the direction bit for that pin to "0" (input mode). Any pin used as an output pin for peripheral functions is directed for output no matter how the corresponding direction bit is set.
(1) Port Pi Direction Register (PDi Register, i, 4 to 9)
Figure 1.18.6 shows the direction registers. This register selects whether the I/O port is to be used for input or output. The bits in this register correspond one for one to each port. No direction register bit for P85 is available.
(2) Port Pi Register (Pi Register, i = 1, 4 to 9)
Figure 1.18.7 show the Pi registers. Data input/output to and from external devices are accomplished by reading and writing to the Pi register. The Pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. For ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register, and data can be written to the port latch by writing to the Pi register. For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and data can be written to the port latch by writing to the Pi register. The data written to the port latch is output from the pin. The bits in the Pi register correspond one for one to each port.
(3) Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
Figure 1.18.8 shows the PUR0 to PUR2 registers. The PUR0 to PUR2 register bits can be used to select whether or not to pull the corresponding port high in 4 bit units. The port chosen to be pulled high has a pull-up resistor connected to it when the direction bit is set for input mode.
(4) Port Control Register
Figure 1.18.9 shows the port control register. When the P1 register is read after setting the PCR register's PCR0 bit to "1", the corresponding port latch can be read no matter how the PD1 register is set.
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M16C/6S Group
Programmable I/O Ports
Direction register
IT800
P40, P42, P56
Data bus
Port latch
Direction register
P53, P54
Data bus
Port latch
IT800
Pull-up selection
P15
Port P1 control register Data bus Port latch
(Note 1)
Input to respective peripheral functions
Pull-up selection
Direction register
P60, P64, P73, P74, P76, P80, P81, P90, P92
"1"
Output Data bus Port latch
(Note 1)
Input to respective peripheral functions
Note 1:
symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc.
Figure 1.18.1. I/O Ports (1) Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 138 of 190
M16C/6S Group
Programmable I/O Ports
Pull-up selection Direction register
"1"
P61, P65
Output
Data bus
Port latch Switching between CMOS and Nch Input to respective peripheral functions (Note 1)
Pull-up selection P83, P84 Direction register
Data bus
Port latch (Note 1)
Input to respective peripheral functions
Pull-up selection Direction register P91
Data bus
Port latch (Note 1)
Input to respective peripheral functions
Note 1:
symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc.
Figure 1.18.2. I/O Ports (2) Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 139 of 190
M16C/6S Group
Programmable I/O Ports
Pull-up selection Direction register P62, P66, P71
Data bus
Port latch (Note 1)
Switching between CMOS and Nch
Input to respective peripheral functions
Pull-up selection P63, P67 Direction register
"1"
Data bus
Port latch
Output
(Note 1)
Switching between CMOS and Nch
P85 Data bus (Note 1)
P70
Direction register
"1"
Output
Data bus
Port latch (Note 2)
Input to respective peripheral functions
Note 1:
symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Note 2: symbolizes a parasitic diode.
Figure 1.18.3. I/O Ports (3) Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 140 of 190
M16C/6S Group
Programmable I/O Ports
Direction register "1"
IT800
P95, P96
Output Data bus Port latch
Direction register
P82, P97, P41
Data bus
Port latch
Input to respective peripheral functions
IT800
Direction register
Testing signal
P10, P11
Data bus
Port latch
Figure 1.18.4. I/O Ports (4)
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M16C/6S Group
Programmable I/O Ports
CNVSS CNVSS signal input
(Note 2) (Note 1)
RESET RESET signal input (Note 1) symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Note 2: A parasitic diode on the V CC side is added to the mask ROM version. Make sure the input voltage on each port will not exceed Vcc. Note 1:
Figure 1.18.5. I/O Pins
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Programmable I/O Ports
Port Pi direction register (i=1, 4 to 7 and 9) (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PD1 PD4 to PD7 PD9 Bit symbol
PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7
Address (Note 2) 03E316 03EA16, 03EB16, 03EE16, 03EF16 03F316 Bit name Function
After reset 0016 0016 0016 RW RW RW RW RW RW RW RW RW
Port Pi0 direction bit Port Pi1 direction bit Port Pi2 direction bit Port Pi3 direction bit Port Pi4 direction bit Port Pi5 direction bit Port Pi6 direction bit Port Pi7 direction bit
0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 7 and 9 to 13)
Note 1: Make sure the PD9 register is written to by the next instruction after setting the PRCR register's PRC2 bit to "1" (write enabled). Note 2: Set PD1_0 and PD1_1 bits to "0."
Port P8 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD8
Address 03F216 Bit name
Port P80 direction bit Port P81 direction bit Port P82 direction bit Port P83 direction bit
After reset 00X000002 Function RW RW RW RW RW RW
Bit symbol
PD8_0 PD8_1 PD8_2 PD8_3 PD8_4 (b5) PD8_6 PD8_7
0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port)
Port P84 direction bit Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. Port P86 direction bit Port P87 direction bit 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port)
RW RW
Figure 1.18.6. PD1, PD4 to PD9 Registers
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M16C/6S Group
Programmable I/O Ports
Port Pi register (i=1, 4 to 7 and 9)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P1 P4 to P7 P9 Bit symbol
Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7
Address (Note 2) 03E116 03E816, 03E916, 03EC16, 03ED16 03F116 Bit name
Port Pi0 bit Port Pi1 bit Port Pi2 bit Port Pi3 bit Port Pi4 bit Port Pi5 bit Port Pi6 bit Port Pi7 bit
After reset Indeterminate Indeterminate Indeterminate Function RW RW RW RW RW RW RW RW RW
The pin level on any I/O port which is set for input mode can be read by reading the corresponding bit in this register. The pin level on any I/O port which is set for output mode can be controlled by writing to the corresponding bit in this register 0 : "L" level 1 : "H" level (Note 1) (i = 0 to 7 and 9 to 13)
Note 1: Since P70 is N-channel open drain ports, the data is high-impedance. Note 2: Set P1_0 and P1_1 bits to "0."
Port P8 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P8 Bit symbol
P8_0 P8_1 P8_2 P8_3 P8_4 P8_5 P8_6 P8_7
Address 03F016 Bit name
Port P80 bit Port P81 bit Port P82 bit Port P83 bit Port P84 bit Port P85 bit Port P86 bit Port P87 bit
After reset Indeterminate Function
The pin level on any I/O port which is set for input mode can be read by reading the corresponding bit in this register. The pin level on any I/O port which is set for output mode can be controlled by writing to the corresponding bit in this register (except for P85) 0 : "L" level 1 : "H" level
RW RW RW RW RW RW RO RW RW
Figure 1.18.7. P1, P4 to P9
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M16C/6S Group
Programmable I/O Ports
Pull-up control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR0 Bit symbol
(b2-b0)
Address 03FC16 Bit name
When read, its content is indeterminate.
After reset 0016 Function RW
Nothing is assigned. When write, set to "0". P14 to P17 pull-up 0 : Not pulled high 1 : Pulled high (Note 2)
PU03
RW
(b7-b4)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Note 1: During memory extension and microprocessor modes, the pins are not pulled high although their corresponding register contents can be modified. Note 2: The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high.
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR1 Bit symbol
(b3-b0)
Address 03FD16 Bit name
After reset(Note 5) 000000002 000000102 Function RW
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
PU14 PU15 PU16
P60 to P63 pull-up P64 to P67 pull-up P72 to P73 pull-up (Note 1)
0 : Not pulled high 1 : Pulled high (Note 3)
PU17 P74 to P77 pull-up Note 1: The P7 0 and P71 pins do not have pull-ups. Note 2: During memory extension and microprocessor modes, the pins are not pulled high although the contents of these bits can be modified. Note 3: The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high. Note 4: If the PM01 to PM00 bits are set to "012" (memory expansion mode) or "112" (microprocessor mode) in a program during single-chip mode, the PU11 bit becomes "1". Note 5: The values after hardware reset 1 and 2 are as follows: * 000000002 when input on CNVss pin is "L" * 000000102 when input on CNVss pin is "H" The values after software reset, watchdog timer reset and oscillation stop detection reset are as follows: * 000000002 when PM 01 to PM00 bits of PM0 register are "002" (single-chip mode) * 000000102 when PM 01 to PM00 bits of PM0 register are "012" (memory expansion mode) or "112" (microprocessor mode)
RW RW RW RW
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR2 Bit symbol
PU20 PU21 PU22
(b7-b3)
Address 03FE16 Bit name
P80 to P83 pull-up P84 to P87 pull-up (Note 2) P90 to P93 pull-up
After reset 0016 Function
0 : Not pulled high 1 : Pulled high (Note 1)
RW RW RW RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Note 1: The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high. Note 2: The P8 5 pin does not have pull-up.
Figure 1.18.8. PUR0 to PUR2 Registers
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M16C/6S Group
Programmable I/O Ports
Port control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbpl PCR
Address 03FF16
After reset 0016
Bit symbol
PCR0
Bit name
Port P1 control bit
Function
RW
Operation performed when the P1 register is read 0: When the port is set for input, the input levels of P10 to P17 RW pins are read. When set for output, the port latch is read. 1: The port latch is read regardless of whether the port is set for input or output.
Nothing is assigned. In an attempt to write to these bits, (b7-b1)
write "0". The value, if read, turns out to be "0".
Figure 1.18.9. PCR Register
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M16C/6S Group
Programmable I/O Ports
Table 1.18.1. Unassigned Pin Handling in Single-chip Mode
Pin name Ports P1, P6 to P9 (excluding P85) XOUT (Note 1) P85 VCCA VSSA Connection After setting for input mode, connect every pin to V SS via a resistor(pull-down); or after setting for output mode, leave these pins open. (2, 3, 4) Open Connect via resistor to VCC (pull-up) Connect to VCC Connect to VSS
NOTES: 1. With external clock input to XIN pin. 2. When setting the port for output mode and leave it open, be aware that the port remains in input mode until it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes indeterminate, causing the power supply current to increase while the port remains in input mode. Furthermore, by considering a possibility that the contents of the direction registers could be changed by noise or noise-induced runaway, it is recommended that the contents of the direction registers be periodically reset in software, for the increased reliability of the program. 3. Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins (within 2 cm). 4. When the port P7_0 is set for output mode, make sure a low-level signal is output from the pin. The port P7_0 is N-channel open-drain output.
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M16C/6S Group
Programmable I/O Ports
Microcomputer
Port P1, P6 to P9 (except for P85) (Note 2) (Input mode) * * * (Input mode) (Output mode)
* * *
Open
P85 XOUT VCCA Open VCC
VSSA
VSS
In single-chip mode
Figure 1.18.10. Unassigned Pins Handling
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M16C/6S Group
Electrical Characteristics
Electrical Characteristics
Table 1.19.1. Absolute Maximum Ratings
Symbol
VCC VCCA Supply voltage Analog supply voltage Input voltage VI RESET, CNVSS P60 to P67, P71, P73, P74, P76, P80 to P85, P90 to P92, XIN P70 Output voltage VO P60 to P67, P71, P73, P74, P76, P80 to P84, P90 to P92, XOUT, TS P70 Pd Topr Tstg Power dissipation Operating ambient temperature Storage temperature
Parameter
Condition
VCC=VCCA VCC=VCCA
Rated value
-0.3 to 4.2 -0.3 to 4.2
Unit
V V
-0.3 to VCC+0.3
V
-0.3 to 6.5
V
-0.3 to VCC1+0.3
V
-0.3 to 6.5 500 -20 to 85 (Note 1) -65 to 150
V mW C C
Note 1: Customers desiring -40 C to +85 C version should contact their Renesas technicak support representative .
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M16C/6S Group
Electrical Characteristics
Table 1.19.2. Recommended Operating Conditions (Note 1)
Symbol
VCC Vcc A Vss Vss A Supply voltage Analog supply voltage Supply voltage Analog supply voltage HIGH input voltage VIH P60 to P67, P71, P73, P74, P76, P80 to P84, P90 to P92 XIN, RESET, CNVSS P70 LOW input voltage VIL P60 to P67, P70, P71, P73, P74, P76, P80 to P84, P90 to P92 XIN, RESET, CNVSS HIGH peak output current 0.8VCC1 0 6.5 0.2VCC1 V V 0.8VCC1
Parameter
Min.
3.0
Standard Typ.
3.3 VCC 0 0
Max.
3.6
Unit
V V V V
VCC1
V
I OH (peak)
P60 to P67, P71, P73, P74, P76, P80 to P84, P90 to P92, TS P60 to P67, P71, P73, P74, P76, P80 to P84, P90 to P92, TS P60 to P67, P70, P71, P73, P74, P76, P80 to P84, P90 to P92, TS P60 to P67, P70, P71, P73, P74, P76, P80 to P84, P90 to P92, TS
-10.0
mA
I OH (avg)
HIGH average output current
- 5 .0
mA
I OL (peak)
LOW peak output current
10.0
mA
I OL (avg)
LOW average output current
5.0
mA
f (XIN) f (Ring) f (BCLK) TSU(PLL)
Main clock input oscillation frequency (Note 4) Ring oscillation frequency CPU operation clock PLL frequency synthesizer stabilization wait time
VCC=3.0 to 3.6V
5.12 1 15.36
MHz MHz MHz 50 ms
VCC=3.0V
Note 1: Referenced to VCC = 3.0 to 3.6V at Topr = -20 to 85 C unless otherwise specified. Note 2: The mean output current is the mean value within 100ms. Note 3: The total IOL (peak) for all ports must be 80mA max, the total IOH (peak) for all ports must be -40mA max.
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M16C/6S Group
Electrical Characteristics
Table 1.19.3. Flash Memory Version Electrical Characteristics (Note 1)
Symbol
- - -
Parameter
Erase/Write cycle (Note 3) Word program time (Vcc=3.3V, Topr=25C) Block erase time 8Kbyte block 16Kbyte block 32Kbyte block Flash Memory Circuit Stabilization Wait Time Data retention time (Note 5)
Standard Min. Typ. (Note 2)
75 0.4 0.7 1.2 20
Max
Unit
cycle
100/1000 (Note 4, 6 ) 600 9 9 9 15
s s s s s year
tPS -
Note 1: When not otherwise specified, Vcc = 3.0 to 3.6V; Topr = 0 to 60 C. Note 2: VCC = 3.3V; Topr = 25 C. Note 3: Program and Erase Endurance refers to the number of times a block erase can be performed. If the program and erase endurance is n (n=100, 1,000), each block can be erased n times. For example, if a 8Kbytes block 0 is erased after writing 1 word data 4096 times, each to a different address, this counts as one program and erase endurance. Data cannot be written to the same address more than once without erasing the block. (Rewrite prohibited) Note 4: Maximum number of E/W cycles for which opration is guaranteed. Note 5: Topr = 55C. Note 6: The program area for U3 and U5 is 100 E/W cycles; the program area for U7 and U9 is 1,000 E/W cycles. Note 7: Customers desiring E/W failure rate information should contact their Renesas technical support representative.
Table 1.19.4. Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics (at Topr = 0 to 60oC)
Flash program, erase voltage VCC = 3.3 V 0.3 V
Flash read operation voltage VCC = 3.0 to 3.6 V
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Electrical Characteristics
Table 1.19.5. Power Supply Circuit Timing Characteristics
Symbol
td(P-R) td(R-S) td(M-L)
Parameter
Time for internal power supply stabilization during powering-on STOP release time Time for internal power supply stabilization when main clock oscillation starts
Measuring condition
Min.
Standard Typ.
Max.
2 150 50
Unit
ms s s
VCC =3.0 to 3.6V
Note : When Vcc1 = 5V
Interrupt for stop mode release CPU clock
td(R-S)
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Electrical Characteristics
Table 1.19.6. Electrical Characteristics (Note)
Symbol
HIGH output voltage HIGH output voltage LOW output voltage
Parameter
P60 to P67, P71, P73, P74, P76, P80 to P84, P90 to P92, TS XOUT
Measuring condition
Standard Min.
VCC-0.5 VCC-0.5
Typ.
Max.
VCC VCC
Unit
V V
VOH VOH VOL VOL
IOH= -1mA IOH= -0.1mA IOL=1mA IOL=0.1mA
P60 to P67, P71, P73, P74, P76, P80 to P84, P90 to P92, TS XOUT TA0IN, TA1IN, TA4IN, INT1 to INT3, CTS0 to CTS SCL, SDA, 2, CLK0 to CLK4, TA4OUT, RxD0 to RxD2, SIN3
0.5 0.5
V V
LOW output voltage Hysteresis
VT+-VT-
0.2
0.8
V
VT+-VT-
Hysteresis HIGH input current
RESET P60 to P67, P70, P71, P73, P74, P76, P80 to P84, P90 to P92 XIN, RESET, CNVss
0.2
(0.7)
1.8
V
IIH
VI=3V
4.0
A
LOW input current
P60 to P67, P70, P71, P73, P74, P76, P80 to P84, P90 to P92 XIN, RESET, CNVss VI=0V
-4.0
A
IIL
RPULLUP
Pull-up resistance
P60 to P67, P71, P73, P74, P76, P80 to P84, P90 to P92 VI=0V 66 160 3.0 500 k M
RfXIN
Feedback resistance
XIN
Note : Referenced to VCC= 3.0 to 3.6V, VSS=0V at Topr = -20 to 85 C , f(BCLK)=15.36 MHz unless otherwise specified.
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Electrical Characteristics
Table 1.19.7. Electrical Characteristics (2) (Note 1)
Symbol Parameter
In single-chip mode, the output pins are open and other pins are VSS
Flash memory Flash memory Program Flash memory Erase
Measuring condition
f(BCLK)=15.36 MHz, No division f(BCLK)=10MHz, Vcc1=3.0V f(BCLK)=10MHz, Vcc1=3.0V
Min.
Standard Typ.
70 TBD TBD
Max.
Unit
mA mA mA
ICC
Power supply current (VCC=2.7 to 3.6V)
Note 1: Referenced to VCC= 3.0 to 3.6V, VSS=0V at Topr = -20 to 85 C , f(BCLK)=15.36 MHz unless otherwise specified.
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Electrical Characteristics
Timing Requirements (VCC = 3V, VSS = 0V, at Topr = - 20 to 85oC unless otherwise specified)
Table 1.19.8. External Clock Input
Symbol
tc tw(H) tw(L) tr tf
Parameter
External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time
Standard Min. Max.
195.3 80 80 18 18
Unit
ns ns ns ns ns
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Electrical Characteristics
Timing Requirements (VCC = 3V, VSS = 0V, at Topr = - 20 to 85oC unless otherwise specified)
Table 1.19.9. Timer A Input (Counter Input in Event Counter Mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 150 60 60 Unit ns ns ns
Table 1.19.10. Timer A Input (Gating Input in Timer Mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 600 300 300 Unit ns ns ns
Table 1.19.11. Timer A Input (External Trigger Input in One-shot Timer Mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. 300 150 150 Max. Unit ns ns ns
Table 1.19.12. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 150 150 Unit ns ns
Table 1.19.13. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Max. Min. 3000 1500 1500 600 600 Unit ns ns ns ns ns
Table 1.19.14. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Symbol tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiIN input cycle time TAiOUT input setup time TAiIN input setup time Parameter Standard Max. Min. 2 500 500 Unit s ns ns
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Electrical Characteristics
Timing Requirements (VCC = 3V, VSS = 0V, at Topr = - 20 to 85oC unless otherwise specified) Table 1.19.15. Serial I/O
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time 0 100 90 Parameter Standard Min. 300 150 150 160 Max. Unit ns ns ns ns ns ns ns
_______
Table 1.19.16. External Interrupt INTi Input
Symbol tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width Parameter Standard Min. 380 380 Max. Unit ns ns
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Electrical Characteristics
tc(TA) tw(TAH) TAi IN input tw(TAL) tc(UP) tw(UPH) TAi OUT input tw(UPL) TAi OUT input (Up/down input) During event counter mode TAi IN input
(When count on falling edge is selected)
th(TIN-UP)
tsu(UP-TIN)
TAi IN input
(When count on rising edge is selected)
Two-phase pulse input in event counter mode TAi IN input tsu(TAIN-TAOUT) TAi OUT input
tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) tsu(TAOUT-TAIN)
Figure 1.19.1. Timing Diagram (1)
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M16C/6S Group
Electrical Characteristics
tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C-Q) RxDi tw(INL) INTi input tw(INH) tsu(D-C) th(C-D) th(C-Q)
Figure 1.19.2. Timing Diagram (2)
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M16C/6S Group
Flash Memory Version
Flash Memory Version
Flash Memory Performance
The flash memory version has three modes--CPU rewrite, standard serial input/output, and parallel input/ output modes--in which its internal flash memory can be operated on. Note: About the parallel writter of exclusive use, there is no schedule of development at the present time. Table 1.20.1 shows the outline performance of flash memory version (see Table 1.1.1 for the items not listed in Table 1.20.1.).
Table 1.20.1. Flash Memory Version Specifications
Item Flash memory operating mode Erase block Program method Erase method Program, erase control method Protect method Number of commands Program/Erase Endurance(Note) Data Retention ROM code protection
Block 0 to 5 (program area)
Specification 2 modes (CPU rewrite, standard serial I/O) See Figure 20.2.1 to 20.2.3 Flash Memory Block Diagram In units of word Block erase Program and erase controlled by software command The block 0 and block 1 are write protected by bit FMR02. 5 commands 100 times 1,000 times (Option)
20 years (Topr = 55C) Standard serial I/O mode is supported.
Note: Program and erase endurance definition Program and erase endurance are the erase endurance of each block. If the program and erase endurance are n times (n=100,1,000), each block can be erased n times. For example, if a 8-Kbyte block 0 is erased after writing 1 word data 4096 times, each to different addresses, this is counted as one program and erasure. However, data cannot be written to the same address more than once without erasing the block. (Rewrite disabled)
Table 1.20.2. Flash Memory Rewrite Modes Overview Flash memory rewrite mode Function CPU rewrite mode The user ROM area is rewritten by executing software commands from the CPU. EW0 mode: Can be rewritten in any area other than the flash memory EW1 mode: Can be rewritten in the flash memory User ROM area Standard serial I/O mode The user ROM area is rewritten by using a dedicated serial programmer. Standard serial I/O mode 1: Clock sync serial I/O Standard serial I/O mode 2: UART
Areas which can be rewritten Operation mode
User ROM area
ROM programmer
Single chip mode Boot mode Memory expansion mode (EW0 mode) Boot mode (EW0 mode) None Serial programmer
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Flash Memory Version
1. Memory Map
The ROM in the flash memory version is separated between a user ROM area and a boot ROM area. Figure 1.20.1 shows the block diagram of flash memory. The user ROM area is divided into several blocks, so that memory can be erased one block at a time. The user ROM area can be rewritten in all of CPU rewrite, standard serial input/output, and parallel input/output modes. The boot ROM area is located at addresses that overlap the user ROM area, and can only be rewritten in parallel input/output mode.
0E800016
Block 4 : 32K bytes
0EFFFF16 0F000016
Block 3 : 32K bytes
0F7FFF16 0F800016 Block 2 : 16K bytes 0FBFFF16 0FC00016 Block 1 : 8K bytes 0FDFFF16 0FE00016 Block 0 : 8K bytes 0FFFFF16 User ROM area 0FF00016 0FFFFF16 4K bytes Boot ROM area (Reserved)
Note 1: To specify a block, use an even address in that block. Note 2: Blocks 0 and 1 can be rewritten if FMR02 of FMR0 register is set to "1" (only in case of CPU rewriting mode.)
Figure 1.20.1. Flash Memory Block Diagram
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M16C/6S Group
Flash Memory Version
Boot Mode
After a hardware reset which is performed by applying a high-level signal to the CNVSS and P15 pins, the microcomputer is placed in boot mode, thereby executing the program in the boot ROM area. The boot ROM area contains a standard serial input/output mode based rewrite control program which was stored in it when shipped from the factory.
Functions To Prevent Flash Memory from Rewriting
To prevent the flash memory from being read or rewritten easily, parallel input/output mode has a ROM code protect and standard serial input/output mode has an ID code check function.
* ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten during parallel input/output mode. Figure 1.20.2 shows the ROMCP register. The ROMCP register is located in the user ROM area.The ROMCP1 bit consists of two bits. The ROM code protect function is enabled by clearing one or both of two ROMCP1 bits to "0" when the ROMCR bits are not `002,' with the flash memory thereby protected against reading or rewriting. Conversely, when the ROMCR bits are `002' (ROM code protect removed), the flash memory can be read or rewritten. Once the ROM code protect function is enabled, the ROMCR bits cannot be changed during parallel input/output mode. Therefore, use standard serial input/output or other modes to rewrite the flash memory.
* ID Code Check Function
Use this function in standard serial input/output mode. Unless the flash memory is blank, the ID codes sent from the programmer and the ID codes written in the flash memory are compared to see if they match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Prepare a program in which the ID codes are preset at these addresses and write it in the flash memory.
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M16C/6S Group
Flash Memory Version
ROM code protect control address
b7 b6 b5 b4 b3 b2 b1 b0
1
1
1
1
Symbol ROMCP
Address 0FFFFF16
Value when shipped FF16 (Note 4)
Bit symbol
Bit name Reserved bit Reserved bit Reserved bit Reserved bit
Function Set this bit to "1" Set this bit to "1" Set this bit to "1" Set this bit to "1"
b5 b4
RW RW RW RW RW RW RW RW RW
ROMCR
ROM code protect reset bit (Note 2, Note 4)
00: Removes protect 01: 10: Enables ROOMCP1 bit 11:
} }
ROMCP1
ROM code protect level 1 set bit (Note 1, Note 3, Note 4)
b7 b6
00: Protect enabled 01: 10: 11: Protect disabled
Note 1: If the ROMCR bits are set to other than `002' and the ROMCP1 bits are set to other than `112' ( ROM code protect enabled), the flash memory is disabled against reading and rewriting in parallel input/output mode. Note 2: If the ROMCR bits are set to `002' when the ROMCR bits are other than `002' and the ROMCP1 bits are other than `112,' ROM code protect level 1 is removed. However, because the ROMCR bits cannot be modified during parallel input/output mode, they need to be modified in standard serial input/output or other modes. Note 3: The ROMCP1 bits are effective when the ROMCR bits are `012,' `102,' or `112.' Note 4: Once any of these bits is cleared to "0", it cannot be set back to "1". If a memory block that contains the ROMCP register is erased, the ROMCP register is set to `FF16.'
Figure 1.20.2. ROMCP Register
Address 0FFFDF16 to 0FFFDC16 ID1 0FFFE316 to 0FFFE016 0FFFE716 to 0FFFE416 0FFFEB16 to 0FFFE816 ID3 ID2
Undefined instruction vector
Overflow vector BRK instruction vector Address match vector Single step vector Watchdog timer vector DBC vector Reserved
0FFFEF16 to 0FFFEC16 ID4 0FFFF316 to 0FFFF016 0FFFF716 to 0FFFF416 0FFFFB16 to 0FFFF816 0FFFFF16 to 0FFFFC16 ID5 ID6 ID7
ROMCP Reset vector
4 bytes
Figure 1.20.3. Address for ID Code Stored Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 163 of 190
M16C/6S Group
Flash Memory Version
CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-board without having to use a ROM programmer, etc. In CPU rewrite mode, only the user ROM area shown in Figure 1.20.1 can be rewritten and the boot ROM area cannot be rewritten. Make sure the Program and the Block Erase commands are executed only on each block in the user ROM area. During CPU rewrite mode, the user ROM area be operated on in either Erase Write 0 (EW0) mode or Erase Write 1 (EW1) mode. Table 1.21.1 lists the differences between Erase Write 0 (EW0) and Erase Write 1 (EW1) modes. Table 1.21.1. EW0 Mode and EW1 Mode Item EW0 mode Operation mode * Single chip mode Areas in which a * User ROM area rewrite control program can be located Areas in which a Must be transferred to any area other rewrite control than the flash memory (e.g., RAM) program can be executed before being executed Areas which can be User ROM area rewritten
EW1 mode Single chip mode User ROM area
Can be executed directly in the user ROM area User ROM area However, this does not include the area in which a rewrite control program exists * Program, Block Erase command Cannot be executed on any block in which a rewrite control program exists * Read Status Register command Cannot be executed Read Array mode Hold state (I/O ports retain the state in which they were before the command was executed)(Note) Read the FMR0 register's FMR00, FMR06, and FMR07 bits in a program
Software command limitations
None
Modes after Program or Erase CPU status during Auto Write and Auto Erase Flash memory status detection
Read Status Register mode Operating
* Read the FMR0 register's FMR00, FMR06, and FMR07 bits in a program * Execute the Read Status Register command to read the status register's SR7, SR5, and SR4 flags. _______ Note: Make sure no interrupts (except NMI and watchdog timer interrupts) and DMA transfers will occur.
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Flash Memory Version
* EW0 Mode
The microcomputer is placed in CPU rewrite mode by setting the FMR0 register's FMR01 bit to "1" (CPU rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register's FMR11 bit = 0, EW0 mode is selected. The FMR01 bit can be set to "1" by writing "0" and then "1" in succession. Use software commands to control program and erase operations. Read the FMR0 register or status register to check the status of program or erase operation at completion.
* EW1 Mode
EW1 mode is selected by setting FMR11 bit to "1" (by writing "0" and then "1" in succession) after setting the FMR01 bit to "1" (by writing "0" and then "1" in succession). Read the FMR0 register to check the status of program or erase operation at completion. The status register cannot be read during EW1 mode. When an erase/program operation is initiated the CPU halts all program execution until the operation is completed.
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M16C/6S Group
Flash Memory Version
Figure 1.21.2 shows the FMR0 and FMR1 registers.
FMR00 Bit
This bit indicates the operating status of the flash memory. The bit is "0" when the Program or Erase is running; otherwise, the bit is "1".
FMR01 Bit
The microcomputer is made ready to accept commands by setting the FMR01 bit to "1" (CPU rewrite mode).
FMR02 Bit
When FMR02 bit is "0" (rewriting is disable), block 0 and block 1 do not receive the command of a program and block erase.
FMSTP Bit
This bit is provided for initializing the flash memory control circuits, as well as for reducing the amount of current consumed in the flash memory. The internal flash memory is disabled against access by setting the FMSTP bit to "1". Therefore, the FMSTP bit must be written to by a program in other than the flash memory. In the following cases, set the FMSTP bit to "1": * When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit not reset to "1" (ready))
FMR06 Bit
This is a read-only bit indicating the status of auto program operation. The bit is set to "1" when a program error occurs; otherwise, it is cleared to "0". For details, refer to the description of the full status check.
FMR07 Bit
This is a read-only bit indicating the status of auto erase operation. The bit is set to "1" when an erase error occurs; otherwise, it is cleared to "0". For details, refer to the description of the full status check. Figure 1.21.3 and 1.21.4 show the setting and resetting of EW0 mode and EW1 mode, respectively.
FMR11 Bit
Setting this bit to "1" places the microcomputer in EW1 mode.
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M16C/6S Group
Flash Memory Version
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR0 Bit symbol FMR00 FMR01
Address
01B716
After reset
XX0000012
0
0
Bit name
RY/BY status flag CPU rewrite mode select bit (Note 1)
Function
0: Busy (being written or erased) 1: Ready 0: Disables CPU rewrite mode 1: Inables CPU rewrite mode 0: Inables lock bit 1: Disables lock bit 0: Enables flash memory operation 1: Stops flash memory operation (placed in low power mode, flash memory initialized) Must always be set to "0" 0: Terminated normally 1: Terminated in error 0: Terminated normally 1: Terminated in error
RW RO
RW
FMR02
Lock bit disable select bit (Note 2)
RW
FMSTP
Flash memory stop bit (Note 3, Note 5))
RW RW RO RO
(b5-b4) FMR06 FMR07
Reserved bit Program status flag (Note 4) Erase status flag (Note 4)
Note 1: To set this bit to "1", write "0" and then "1" in succession. Make sure no interrupts or DMA transfers will occur before writing "1" after writing "0". Also, while in EW0 mode, write to this bit from a program in other than the flash memory. Note 2: To set this bit to "1", write "0" and then "1" in succession when the FMR01 bit = 1. Make sure no interrupts or no DMA transfers will occur before writing "1" after writing "0". Note 3: Write to this bit from a program in other than the flash memory. Note 4: This flag is cleared to "0" by executing the Clear Status command. Note 5: Effective when the FMR01 bit = 1 (CPU rewrite mode). If the FMR01 bit = 0, although the FMR03 bit can be set to "1" by writing "1" in a program, the flash memory is neither placed in low power mode nor initialized.
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR1 Bit symbol (b0) FMR11
Address
01B516
After reset
0X00XX0X2
0
0
0
0
Bit name
Reserved bit EW1 mode select bit ( Note) Reserved bit Reserved bit
Function
The value in this bit when read is indeterminate. 0: EW0 mode 1: EW1 mode The value in this bit when read is indeterminate. Must always be set to "0"
RW RO RW RO RW
(b3-b2) (b5-b4) (b6) (b7)
Nothing is assigned. When write, set to "0". When read, their contents are indeterminate. Reserved bit Must always be set to "0"
RW
Note : To set this bit to "1", write "0" and then "1" in succession when the FMR01 bit = 1. Make sure no interrupts or no DMA transfers will occur before writing "1" after writing "0". The FMR01 and FMR11 bits both are cleared to "0" by setting the FMR01 bit to "0".
Figure 1.21.2. FIDR Register and FMR0 and FMR1 Registers
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M16C/6S Group
Flash Memory Version
EW0 mode operation procedure
Rewrite control program Single-chip mode Set the FMR01 bit by writing "0" and then "1" (CPU rewrite mode enabled) (Note 2)
Set CM0, CM1, and PM1 registers (Note1)
Execute software commands
Transfer a CPU rewrite mode based rewrite control program to any area other than the flash memory
Execute the Read Array command
Jump to the rewrite control program which has been transferred to any area other than the flash memory (The subsequent processing is executed by the rewrite control program in any area other than the flash memory)
Write "0" to the FMR01 bit (CPU rewrite mode disabled)
Jump to a specified address in the flash memory
Note 1: Select 10 MHz or less for CPU clock using the CM0 register's CM06 bit and CM1 register's CM17 to 6 bits. Also, set the PM1 register's PM17 bit to "1" (with wait state). Note 2: To set the FMR01 bit to "1", write "0" and then "1" in succession. Make sure no interrupts or no DMA transfers will occur before writing "1" after writing "0". Write to the FMR01 bit from a program in other than the flash memory. Note 3: Disables the CPU rewrite mode after executing the Read Array command.
Figure 1.21.3. Setting and Resetting of EW0 Mode
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M16C/6S Group
Flash Memory Version
EW1 mode operation procedure Program in ROM
Single-chip mode
Set CM0, CM1, and PM1 registers (Note 1)
Set the FMR01 bit by writing "0" and then "1" (CPU rewrite mode enabled) Set the FMR11 bit by writing "0" and then "1" (EW1 mode) (Note 2)
Execute software commands
Write "0" to the FMR01 bit (CPU rewrite mode disabled)
Note 1: Select 10 MHz or less for CPU clock using the CM0 register's CM06 bit and CM1 register's CM17 to 6 bits. Also, set the PM1 register's PM17 bit to "1" (with wait state). Note 2: To set the FMR01 bit to "1", write "0" and then "1" in succession. Make sure no interrupts or no DMA transfers will occur before writing "1" after writing "0". Write to the FMR01 bit from a program in other than the flash memory. Also write only when the NMI pin is "H" level.
Figure 1.21.4. Setting and Resetting of EW1 Mode
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M16C/6S Group
Flash Memory Version
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation Speed Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for BCLK using the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register. Also, set the PM17 bit in the PM1 register to "1" (with wait state). (2) Instructions to Prevent from Using The following instructions cannot be used in EW0 mode because the flash memory's internal data is referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction (3) Interrupts EW0 Mode * Any interrupt which has a vector in the variable vector table can be used providing that its vector is transferred into the RAM area. _______ * The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 register are initialized when one of those interrupts occurs. The jump addresses for those interrupt service routines should be set in the fixed vector table. _______ Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine. * The address match interrupt cannot be used because the flash memory's internal data is referenced. EW1 Mode * Make sure that any interrupt which has a vector in the variable vector table or address match interrupt will not be accepted during the auto program or auto erase period. * Avoid using watchdog timer interrupts. * The WDT interrupt can be used because the FMR0 register and FMR1 register are initialized when this interrupt occurs. The jump address for the interrupt service routine should be set in the fixed vector table. Because the rewrite operation is halted when a WDT interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine. (4) How to Access To set the FMR01, FMR02, or FMR11 bit to "1", write "0" and then "1" in succession. This is necessary to ensure that no interrupts or DMA transfers will occur before writing "1" after writing "0". (5) Writing in the User ROM Space EW0 Mode * If the power supply voltage drops while rewriting any block in which the rewrite control program is stored, a problem may occur that the rewrite control program is not correctly rewritten and, consequently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial I/O or parallel I/O mode should be used. EW1 Mode * Avoid rewriting any block in which the rewrite control program is stored. Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 170 of 190
M16C/6S Group
Flash Memory Version
(6) DMA Transfer In EW1 mode, make sure that no DMA transfers will occur while the FMR0 register's FMR00 bit = 0 (during the auto program or auto erase period). (7) Writing Command and Data Write the command code and data at even addresses. (8) Wait Mode When shifting to wait mode, set the FMR01 bit to "0" (CPU rewrite mode disabled) before executing the WAIT instruction. (9) Stop Mode When shifting to stop mode, the following settings are required: * Set the FMR01 bit to "0" (CPU rewrite mode disabled) and disable DMA transfers before setting the CM10 bit to "1" (stop mode). * Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to "1" (stop mode) Example program BSET 0, CM1 ; Stop mode JMP.B L1 L1: Program after returning from stop mode
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Flash Memory Version
Software Commands
Software commands are described below. The command code and data must be read and written in 16bit units, to and from even addresses in the user ROM area. When writing command code, the 8 highorder bits (D1t-D8) are ignored. Table 1.21.2. Software Commands
First bus cycle Command Read array Read status register Clear status register Program Block erase Mode Write Write Write Write Write Address X X X WA X Data (D0 to D7) xxFF16 xx7016 xx5016 xx4016 xx2016 Write Write WA BA WD xxD016 Read X SRD Mode Second bus cycle Address Data (D0 to D7)
SRD: Status register data (D7 to D0) WA: Write address (Make sure the address value specified in the the first bus cycle is the same even address as the write address specified in the second bus cycle.) WD: Write data (16 bits) BA: Uppermost block address (even address, however) X: Any even address in the user ROM area x: High-order 8 bits of command code (ignored)
Read Array Command (FF16) This command reads the flash memory. Writing `xxFF16' in the first bus cycle places the microcomputer in read array mode. Enter the read address in the next or subsequent bus cycles, and the content of the specified address can be read in 16-bit units. Because the microcomputer remains in read array mode until another command is written, the contents of multiple addresses can be read in succession. However, when you use Read array command immediately after a program command, please read data in the following procedure. (1) FF16, FF16, FF16, and FF16 are written to 4 arbitrary continuous addresses. (2) The head address of (1) is specified in Read array mode. (3) (2) is repeated until the read value and FFFF16 are in agreement. (4) The head address +2 of (1) is specified. (5) (4) is repeated until the read value and FFFF16 are in agreement. (6) Arbitrary addresses are specified. Read Status Register Command (7016) This command reads the status register. Write `xx7016' in the first bus cycle, and the status register can be read in the second bus cycle. (Refer to "Status Register.") When reading the status register too, specify an even address in the user ROM area. Do not execute this command in EW1 mode.
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Flash Memory Version
Clear Status Register Command (5016) This command clears the status register to "0". Write `xx5016' in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to SR5 in the status register will be cleared to "0". Program Command (4016) This command writes data to the flash memory in 1 word (2 byte) units. Write `xx4016' in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the same even address as the write address specified in the second bus cycle. Check the FMR00 bit in the FMR0 register to see if auto programming has finished. The FMR00 bit is "0" during auto programming and set to "1" when auto programming is completed. Check the FMR06 bit in the FMR0 register after auto programming has finished, and the result of auto programming can be known. (Refer to "Full Status Check.") Writing over already programmed addresses is inhibited. Moreover, when FMR02 bit of FMR0 register is "0" (rewriting is disable), the program command to block 0 and block 1 is not received. Just behind a program command, when you execute commands other than a program command, please make it the address value which was specified by the 2nd bus cycle of a program command and which writes in and specifies the same address as an address by the 1st bus cycle of the following command. In EW1 mode, do not execute this command on any address at which the rewrite control program is located. In EW0 mode, the microcomputer goes to read status register mode at the same time auto programming starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to "0" at the same time auto programming starts, and set back to "1" when auto programming finishes. In this case, the microcomputer remains in read status register mode until a read command is written next. The result of auto programming can be known by reading the status register after auto programming has finished.
Start Write the command code `xx4016' to the write address Write data to the write address
FMR00=1? YES Full status check
NO
Program completed Note: Write the command code and data at even number.
Figure 1.21.5. Program Command Rev.4.00 Aug 05, 2005 REJ03B0014-0400 page 173 of 190
M16C/6S Group
Flash Memory Version
Block Erase Write `xx2016' in the first bus cycle and write `xxD016' to the uppermost address of a block (even address, however) in the second bus cycle, and an auto erase operation (erase and verify) will start. Check the FMR0 register's FMR00 bit to see if auto erasing has finished. The FMR00 bit is "0" during auto erasing and set to "1" when auto erasiing is completed. Check the FMR0 register's FMR07 bit after auto erasing has finished, and the result of auto erasing can be known. (Refer to "Full Status Check.") Moreover, when FMR02 bit of FMR0 register is "0" (rewriting is disable), the block erase command to block 0 and block 1 is not received. Figure 1.21.6 shows an example of a block erase flowchart. Each block can be protected against erasing by a lock bit. (Refer to "Data Protect Function.") Writing over already programmed addresses is inhibited. In EW1 mode, do not execute this command on any address at which the rewrite control program is located. In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to "0" at the same time auto erasing starts, and set back to "1" when auto erasing finishes. In this case, the microcomputer remains in read status register mode until the Read Array or Read Lock Bit Status command is written next.
Start
Write the command code `xx2016' Write `xxD016' to the uppermost block address
FMR00=1? YES Full status check
NO
Block erase completed Note: Write the command code and data at even number.
Figure 1.21.6. Block Erase Command
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Flash Memory Version
Status Register
The status register indicates the operating status of the flash memory and whether an erase or programming operation terminated normally or in error. The status of the status register can be known by reading the FMR0 register's FMR00, FMR06, and FMR07 bits. Table 1.21.3 shows the status register. In EW0 mode, the status register can be read in the following cases: (1) When a given even address in the user ROM area is read after writing the Read Status Register command (2) When a given even address in the user ROM area is read after executing the Program, Block Erase, Erase All Unlocked Block, or Lock Bit Program command but before executing the Read Array command. Sequencer Status (SR7 and FMR00 Bits ) The sequence status indicates the operating status of the flash memory. SR7 = 0 (busy) during auto programming and auto erase is set to "1" (ready) at the same time the operation finishes. Erase Status (SR5 and FMR07 Bits) Refer to "Full Status Check." Program Status (SR4 and FMR06 Bits) Refer to "Full Status Check." Table 1.21.3. Status Register * D0 to D7: Indicates the data bus which is read out when the Read Status Register command is executed. Value FMR0 Status Contents Status name after register register "0" "1" reset bit bit
SR7 (D7) SR6 (D6) SR5 (D5) SR4 (D4) SR3 (D3) SR2 (D2) SR1 (D1) SR0 (D0)
FMR00
Sequencer status Reserved
Busy Terminated normally Terminated normally -
Ready Terminated in error Terminated in error -
1
FMR07 FMR06
Erase status Program status Reserved Reserved Reserved Reserved
0 0
* The FMR07 bit (SR5) and FMR06 bit (SR4) are cleared to "0" by executing the Clear Status Register command. * When the FMR07 bit (SR5) or FMR06 bit (SR4) = 1, the Program and Block Erase are not accepted.
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Flash Memory Version
Full Status Check
When an error occurs, the FMR0 register's FMR06 to FMR07 bits are set to "1", indicating occurrence of each specific error. Therefore, execution results can be verified by checking these status bits (full status check). Table 1.21.4 lists errors and FMR0 register status. Figure 1.21.7 shows a full status check flowchart and the action to be taken when each error occurs. Table 1.21.4. Errors and FMR0 Register Status FMR00 register (SRD register) status FMR07 FMR06 (SR5) (SR4) 1 1
Error
Error occurrence condition
Command * When any commands are not written correctly sequence error * A value other than `xxD016' or `xxFF16' is written in the second bus cycle of the block erase command (Note 1) * When the block erase command is executed on protected blocks * When the program command is executed on protected blocks 1 0 Erase error * When the block erase command is executed on unprotected blocks but the blocks are not automatically erased correctly 0 1 Program error * When the program command is executed on unprotected blocks but the blocks are not automatically programmed correctly. Note 1: The flash memory enters read array mode by writing command code `xxFF16' in the second bus cycle of these commands. The command code written in the first bus cycle becomes invalid.
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Flash Memory Version
Full status check
FMR06 =1 and FMR07=1?
YES
Command sequence error
(1) Execute the Clear Status Register command to clear these status flags to 0 . (2) Reexecute the command after checking that it is entered correctly.
NO NO (1) Execute the Clear Status Register command to clear the erase status flag to 0 . (2) Reexecute the Block Erase command. Note 1: If the error still occurs, the block in error cannot be used.
FMR07= 0? YES
Erase error
FMR06= 0? YES
NO
Program error
[During programming] (1) Execute the Clear Status Register command to clear the erase status flag to 0 . (2) Reexecute the Program command. Note 2: If the error still occurs, the block in error cannot be used.
Full status check completed
Note 3: If FMR06 or FMR07 = 1, neither the Program nor Block Erase command is accepted. Execute the Clear Status Register command before executing those commands.
Figure 1.21.7. Full Status Check and Handling Procedure for Each Error
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Flash Memory Version
Standard Serial I/O Mode
The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory using the serial I/O port UART1. The serial I/O mode transfers the data serially in 8-bit units. In the standard serial I/O mode the CPU executes a control program for flash memory rewrite (using the CPU's rewrite mode), rewrite data input and so forth. It is started when both the P15 (CE) pin and the CNVss pin are in "H" level after the reset is released. (In normal operation mode, set CNVss pin to "L" level.) This control program is written in the boot ROM area when the product is shipped. There are actually two standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Standard serial I/O swiches between mode 1 (clock synchronous) and mode 2 (clock asynchronous) depending on the level of CLK1 pin when the reset is released. To use standard serial I/O mode 1 (clock synchronous), set the CLK1 pin to "H" level and release the reset. The operation uses the four UART1 pins CLK1, RxD1, TxD1 and RTS1 (BUSY). The CLK1 pin is the transfer clock input pin through which an external transfer clock is input. The TxD1 pin is for CMOS output. The RTS1 (BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts. In mode 1, be sure the TxD1 (P67) pin is at high before reset being deasserted. To use standard serial I/O mode 2 (clock asynchronous), set the CLK1 pin to "L" level and release the reset. The operation uses the two UART1 pins RxD1 and TxD1. In standard serial input/output mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a serial programmer suitable for the M16C/62P group. For more information about serial programmers, contact the manufacturer of your serial programmer. For details on how to use, refer to the user's manual included with your serial programmer. Table 1.22.1 lists pin functions (flash memory standard serial input/output mode). Figures 1.22.1 to 1.22.2 show pin connections for serial input/output mode.
ID Code Check Function
This function determines whether the ID codes sent from the serial programmer and those written in the flash memory match. (Refer to the description of the functions to inhibit rewriting flash memory version.)
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Flash Memory Version
Table 1.22.1. Functional explanation of pin (flash memory standard serial I/O mode)
Pin VCC,VSS CNVSS RESET XIN XOUT VDCCN VCCA, VSSA VREF P60 to P63 P64/RTS1 Analog power supply input Standard voltage input Input port P6 BUSY output I I I O Signal name Power supply input CNVSS Reset input I I I/O Description Apply the voltage guaranteed for Program and Erase to Vcc pin. Apply 0 V to Vss pin. Connect to Vcc pin. Reset input pin. While RESET pin is "L" level, input a 20 cycle or longer clock to XIN pin. Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. Input "H" level signal. Please connect AVcc to Vcc and connect AVss to Vss. Input the standard voltage of a preamplifier and an operational amplifier. Input "H" or "L" level signal or open. Standard serial I/O mode 1: BUSY signal output pin Standard serial I/O mode 2: Monitors the boot program operation check signal output pin. Standard serial I/O mode 1: Serial clock input pin Standard serial I/O mode 2: Input "L." Serial data input pin. Serial data output pin. (Note 1) Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" level signal. Input "H" or "L" level signal or open.
Clock input Clock output
I O
P65/CLK1
SCLK input
I
P66/RXD1 P67/TXD1 P70, P71, P73, P74, P76 P80, P81, P83, P84, P85 P15 P90 to P92
RxD input TxD output Input port P7 Input port P8
I O I I
CE input Input port P11
I I
Note 1: When using standard serial input/output mode 1, the TxD pin must be held high while the RESET pin is pulled low. Therefore, connect this pin to Vcc1 via a resistor. Because this pin is directed for data output after reset, adjust the pull-up resistance value in the system so that data transfers will not be affected.
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Flash Memory Version
Example of Circuit Application in the Standard Serial I/O Mode
Figure 1.22.1 and 1.22.2 show example of circuit application in standard serial I/O mode 1 and mode 2, respectively. Refer to the user's manual for serial writer to handle pins controlled by a serial writer.
Microcomputer Clock input Data input BUSY output Data output SCLK P15(CE) TXD BUSY RxD CNVss
Reset input User reset signal
RESET
(1) Control pins and external circuitry will vary according to programmer. For more information, see the programmer manual. (2) In this example, modes are switched between single-chip mode and standard serial input/output mode by controlling the CNVss input with a switch. (3) If in standard serial input/output mode 1 there is a possibility that the user reset signal will go low during serial input/output mode, break the connection between the user reset signal and RESET pin by using, for example, a jumper switch.
Figure 1.22.1. Circuit Application in Standard Serial I/O Mode 1
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Flash Memory Version
Microcomputer SCLK Data output Monitor output Data input TxD BUSY RxD CNVss
P15(CE)
(1) In this example, modes are switched between single-chip mode and standard serial input/output mode by controlling the CNVss input with a switch.
Figure 1.22.2. Circuit Application in Standard Serial I/o Mode 2
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Flash Memory Version
ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten. (Refer to the description of the functions to inhibit rewriting flash memory version.)
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IT800AFE (Analog Front End)
IT800AFE (Analog Front End) 1. The block diagram of analog front end
Analog front end (AFE) part is the circuit located between M16C/6S and a power line, and M16C/6S build in DAC, preamplifier, and ADC. There are the following two signal circuits in AFE. (1)Transmitting circuit:It drives with the signal from the logic of M16C/6S inside, and this is consists of DAC with a differential output, Output filter for spectrum adjustment, Differential line driver amplifier and line coupling circuit which drive power line. (2)Receiving circuit:This is consists of Line coupling circuit, Differential preamplifier, Input filter group and ADC. Line coupling circuit is common to both transmission and reception.
M16C/6S Line Driver DAC Output Filter Line Driver Power line
Channel Filters
ADC
Pre Amp
Input Filter
Fig.1.23.1 Analog Front End circuit block diagram
(1)Transmitting circuit
The characteristic required for transmitting course is as follows. (a)A suitable output signal level is obtained to the load of rating (b)It has the frequency characteristic to maximum zone width of 400kHz (c)The signal level outside a zone:It is less than each regulation This system assumes operation in the following three fundamental signal zones. (a)The U.S., Japan:100k to 400kHz (b)Europe in door:95k to 125kHz(CENELEC B Band) (c)Europe out door:20k to 80kHz(CENELEC A Band) It is necessary to perform the change of a signal zone by change of adjustment of change of the configuration of IT800, the analog filter to a signal zone, or output electric power, and the output impedance of the line driver stage (notes). Note. Please refer to the following standard and style about the conditions outside a signal level or a zone. (a)The U.S.:FCC standard, part 15 (b)Europe:CENELEC standard, EN 50065-1 (c)Japan:ARIB
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IT800AFE (Analog Front End)
About DAC (Digital to Analog Converter)
DAC of built-in in M16C/6S is current output type 10 bit DAC.The standard level of output current can be set up by the external resistance linked to a built-in standard power supply. A DAC circuit and a load circuit are shown in Fig. 1.23.2. The typical characteristic is shown in Table 1.23.1.
10 bit DAC
Iout DATA D9-D0 10 7
Matrix Current Cell
Rout 2.1k(1%)
Cout 33pF
Line Driver Amp
Vref
+
-
6 Ioutc Routc 2.1k(1%) Coutc 33pF
Rext
8 Rext 2.1k(1%)
External pin (pin number) LSI internal connection
IFULL(mA)=2131/Rext() =Iout+Ioutc At Rext=2.1k, IFULL=1mA
Fig.1.23.2 DAC (Digital to Analog Converter)
Table.1.23.1 DAC Electrical Characteristics (Vdd=3.30.3V, Ta=-20C to 85C unless otherwise specified)
Electrical Characteristics Parameter Standard voltage Standard current External standard register DAC output register Full-scale current Maximum output voltage Symbol Vref Iref Rext Rout/Routc IFULL Voutmax Rext=2.1k Rext=2.1k Rout/Routc=2.1k 0.9 1 Condition Rext=2.1k Rext=2.1k Min Typ 0.3 0.14 2.1 2.0 1.1 Vdd-1 Max Unit V mA k k mA V
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IT800AFE (Analog Front End)
In the circumference of a DAC circuit, it is cautious of the following point and a constant is set up. (a)Full-scale output current of DAC Although the current by which DAC is outputted to a pin (Iout/Ioutc) according to the change width of an internal bit changes, total is fixed and serves as full-scale output current (IFULL). This IFULL can be set up by the following formula. IFULL=2131/Rext(mA) The unit of Rext is Since about 1mA of an IFULL value is the optimal value, Rext is 2.1k . DAC is total and Iout/Ioutc changes between 0 to IFULL at 1024 steps by the full range for a change width of 10 bits. The value of Iout/Ioutc is expressed with the following formula if the step value which converted the 10bit binary input into decimal is set to d. (d=0 to 1023) Iout=IFULL/1023*d Ioutc=IFULL/1023*(1023-d) (b)About DAC load resistance Resistance (Rout/Routc) is connected to a DAC output pin.In this resistance, signal voltage occurs by the current (Iout/Ioutc) which flows, respectively. In order to maintain the linearity of Iout/Ioutc, it is necessary to set up Rout/Routc so that this potential may not exceed maximum 2V. Since Iout/Ioutc is mostly set to one half of IFULL(s) at the time of a non-signal (balanced state), the signal voltage (Vout/Voutc) of a DAC output pin is set to below: Vout=Rout X Iout Voutc=Routc X Ioutc Since the recommendation value of Vout/Voutc at the time of a non-signal is about 1V, in Rext=2.1k , Rout/Routc serves as 2.1k . The capacitor (Cout/Coutc) for output filters cuts the high frequency ingredient of DAC, and sets it up on balance with necessary zone frequency.
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IT800AFE (Analog Front End)
(2)Receiving circuit
(a)Preamplifier A preamplifier circuit consists of two CMOS operational amplifiers as shown in Fig. 3, the first opamp is connected as gain stage with gain of 20dB and the second opamp is connected as a voltage follower for driving of external filter.
3.3V 10k Vref 0.1F 10k M16C/6S
Pre-InP
Input filter
Pre-InN
Amplifier Buffer
Pre_BOut
Fig. 1.23.3 Consists of Preamp circuit
Table.1.23.2 Preamp Electrical Characteristics ( Ta=-25C unless otherwise specified)
Electrical Characteristics Parameter Standard voltage Input off-set voltage Open loop gain Gain band width Common mode input range Common mode rejection ratio Power supply rejection ratio Symbol Vdd Vof GVO BW CMIR CMRR PSRR No-load GVO=0dB DC to 1MHz DC to 1MHz DC to 1MHz 70 5 0.7 40 30 Vdd-0.7 Condition Min 3.0 Typ 3.3 Max 3.6 15 Unit V mV dB MHz V dB dB
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IT800AFE (Analog Front End)
(b)ADC (Analog to Digital Converter) The output of the channel filter (maximum of three) connected outside is connected to 1 bit ADC which consists of an operational amplifier and a comparator. M16C/6S build in ADC of three equivalent performances. The circuit of one ADC has composition shown in the following figure.
R1/R2/R3 C1/C2/C3
AMP1_Out/AMP2_Out/ AMP3_Out
CH1_InP/CH2_InP/ CH3_InP
Channel Filter
1k
0.22F
AMP1_IN/ AMP2_IN/ AMP3_IN/
Amplifier
+
Comparator
3.3V 10k
Vref
+
-
0.1F
10k
CH1_InN/CH2_InN/ CH3_InN FB1/FB2/FB3
0.1F
Fig.1.23.4 ADC block diagram
Three ADC use all three by the signal zone to be used. The constant of a filter is set up as shown in the following table.
Table.1.23.3 The example of an ADC part constant setting
Parts Capacitor Parts
Application characteristic FCC/ARIB CECLEC-B Application characteristic FCC/ARIB CECLEC-B
C1 33 33 R1 10 10
C2 22
C3 10
Unit pF pF
R2 10
R3 12
Unit k k
Register
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APPENDIX
APPENDIX
IT800DLL Explanatory Note
June 2, 2005
IT800 Data Link Layer - Functionality and Advantages 1. Scope
This document describes the functionality of the Data Link Layer (DLL) implemented in the products based on Yitran's IT800 technology for narrowband networking using the power line wiring. The purpose of this document is to emphasize the advantages of the embedded algorithms and mechanisms of the DLL and to analyze the scenarios of using other implementations of a Data Link Layer.
2. Network Reference Module
The DLL is the 2nd layer of the 7 layers in the OSI network reference model illustrated in Figure 1(a). According to this model, data is transported upstream and downstream between subsequent layers, where the communication between layers of different communication nodes is basically carried out between the same layers [Figure 1(b)].
Application Presentation Session Transport Network DLL PHY Physical Layers Layer 1 Upper Layers Layer 3 Data Transport Layer 2 STOP Layer 1 Layer 2 Layer Communication
Layer 3
(a) OSI 7 Layers Model
(b) Data Transport and Layer Communication
Figure 1: Network Reference Model The Physical Layer (PHY) defines the electrical specifications for activating, the physical link between the communicating network system nodes. The DLL algorithms are designed to establish and manage a unique access channel between any two nodes as optimally and fairly as possible while minimizing the probability of collisions. The IT800 DLL was developed by Yitran especially for the IT800 PHY and using the DLL optimize the utilization of the PHY and thus optimizes the overall performance. The IT800 DLL implementation manages the time critical sessions of the interface with the PHY and uses the knowledge of the PHY implementation for optimal interrupt decoding and efficient interface interactions. The DLL takes advantage of various PHY features such as multiple transportation modes and the ability to create special packets and signals, enabling optimal utilization of the media channel while providing the most reliable data transfer.
Copyright (c) 2005, YITRAN Communications Ltd. Page 1
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APPENDIX
IT800DLL Explanatory Note
June 2, 2005
3. IT800DLL Main functions
The DLL main functions and mechanisms are described in the following table:
Function Description
Carrier sense
Provides the carrier detection (CD) signal for triggering the media access algorithms as a function of the PHY correlator output, which indicates the probability of a signal on the line. Determines the sequence and time of packet transmissions for a PLC node, where the highest priority packet nodes participate in the DLL contention for the media access. Spreads the time over which a PLC node contends for the channel using a uniform distribution of the transmissions number over a given period of time (Yitran patent pending). This mechanism provides high efficiency of the network functionality, optimal utiliziation of the channel and sustains a viable network even in cases where many nodes contend for the channel simultaneously. Serves for informing the transmitting node about the success or failure of a packet delivery to a target node by means of a traffic-free acknowledgement window. This mechanism is used for transmitting packets a pre-determined number of times without requiring a reception acknowledgement from the target node. Retransmits single-network broadcast packets and CNC (Control Network Channel) messages to all the nodes participating in the same logical network. Transfers packets longer than the maximal packet size allowed by the PHY by means of fragmentation in the transmitting node and reassembly in the receiving node Filters received packets according to their type for transferring only pre-defined types of messages to the upper layers and rejecting impostor node or other types of messages that are not required.
Channel access prioritization Adaptive back-off
Acknowledgement
Repetitive unacknowledgement Multiple hop broadcast
Fragmentation and reassembly Packet filtering
As can be seen from the table above, the IT800 DLL implements enhanced functionality, provides best performance in terms of channel access and throughput (based on Carrier Sense signaling, Adaptive Back-off algorithm and packet prioritization), reliable data transfer (using acknowledgement and repetition mechanisms, multi-hop transmissions and packet filtering) and allows easy integration of IT800 based solution with different protocol stacks. Another important advantage of using IT800DLL is assuring the co-existence between different IT800 based products operating in the same environment.
Copyright (c) 2005, YITRAN Communications Ltd.
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APPENDIX
IT800DLL Explanatory Note
June 2, 2005
4. Other DLL implementations
In case of using other implementations of the DLL or considering such implementations, please be advised to consider the following issues: 1. Co-existence: Implementing a different channel access scheme, prioritization levels, packet formats and so forth, will not allow your product to co-exist with other IT800 based products that may share the same medium. Using the IT800 will enable such co-existence regardless of the product, the vendor, the application and the protocol used in top of the DLL. 2. Required Knowledge, Time to Market and Cost: Interfacing the DLL is much easier than interfacing the PHY. Physical layer interface includes handling of a several interrupts, critical timing sections and so forth. To be able to do so you require very good understanding of the both the power line medium and the PHY internal mechanisms and will significantly increase the development resources and schedule and as a result the time to market and product cost. In addition note that not all the PHY internal mechanism can be disclosed as some are in the status of patent-pending. 3. Overall performance: IT800DLL has been tested and integrated into different Control and Automation products over the last three years. The implementation has showed the best performance for Narrowband Power Line communication modem, when all the algorithms implemented in it were verified using the networking simulations and in real systems.
5. Summary
As a conclusion, we highly recommend to using IT800 DLL implementation in all type of products using the IT800 PHY, rather than using the latter by itself. In case you still wish to self implement the DLL layer, please be sure to consult RENESAS support engineers.
Copyright (c) 2005, YITRAN Communications Ltd.
Page 3
Rev.4.00 Aug 05, 2005 REJ03B0014-0400
page 190 of 190
REVISION HISTORY
Rev. Date Page 1.00 Jun 25, 2003 2.00 Aug 18, 2003 P1 P2 P3 P4 P5 P7 P8 P9 P12 P14 P15 P20 P24 P25 P26 P27 P29 P30 P33 P36 P37 P42 P43 P45 P52 P54 P62 P83 P84 P85 P88 P90 P92 P94 P95 P100 P107 P119 First edition issued L7 is changed. T1.1.1 is changed. F1.1.1 is changed. T1.1.2 is changed. F1.1.2 is changed. T1.1.3 is changed. T1.1.4 is changed. L5 and F1.2.1 are changed. Table of register is changed. Table of register is changed. Table of register is changed. F1.5.2 is changed. F1.6.1 is changed. F1.6.2 is changed. F1.6.3 is changed. L2 and F1.7.1 are changed. F1.7.2 is changed. F1.7.3 is changed. L4 to L5 and F1.7.6 are changed. L5 is changed. T1.7.2 is changed. F1.7.8 is changed. T1.7.6 is changed. T1.7.7 is changed. T1.9.2 is changed. T1.9.3 is changed. L2 is changed. F1.12.5 is changed. F1.12.6 is changed. L3 and T1.12.2 are changed. F1.12.8 is changed. F1.12.9 is changed. F1.12.10 is changed. L13 is changed. F1.13.1 is changed. F1.13.6 is changed. F1.14.2 and F1.14.3 are changed. T1.16.2 is changed.
M16C/6S Group
Description Summary
A- 1
Rev.
Date Page P121 P127 P128 - P139 P140 P141 P143 P147 P149 P151 P152 P153 P154 P155 P157 P158 P159 P162 P163 P164 P166 P169 P170 P171 P174 P175 P176 P177 P178 P179 P181 P182 P183 P184 PT1.16.4 is changed. T1.16.6 is changed. F1.16.5 is changed. Special Mode 3 is delated.
Description Summary
2.00 Aug 18, 2003
L10 to L11 and L17 to L19 and L21 and L30 to L32 and L38 to L40 are changed. F1.18.1 is changed. F1.18.2 is changed. F1.18.4 is changed. F1.18.8 is changed. T1.18.1 is changed. T1.19.1 is changed. T1.19.2 is changed. T1.19.4 is changed. T1.19.5 is changed. T1.19.6 is changed. L2 and T1.19.8 are changed. L2 is changed. L2 is changed. L3 to L4 are delated. T1.20.2 is changed. 1.Memory Map is changed. F1.20.1 is changed. Boot Mode is changed. L5 and T1.21.1 are changed. P168 is changed. F1.21.2 is changed. F1.21.3 is changed. F1.21.4 is changed. T1.21.2 is changed. Read Array Command is changed. Program Command is changed. Block Erase is changed. Sequencer Status and T1.21.3 are changed. T1.21.4 is changed. F1.21.7 is changed. T1.22.1 is changed. F1.22.1 is changed. F1.22.2 is changed. Parallel I/O Mode and User ROM and Boot ROM Areas are delated.
A- 2
Rev.
Date Page P3 P7 P22 P23 P141 P143 P144 P178 P1 P2 P4 P5 P6 P7 P9 P22 P23 P26 P27 P32 P33 P36 P37 P38 P44 P45 P46 P48 P49 P55 P58 P59 Between P60 to P61 P63 P79 P137 P140 P147 P148 P149 P150 P151 P152
Description Summary L1 to L2 are changed. F1.1.1 is changed. T1.1.3 is changed. L3 to L4 are changed. (3) Setting PLC Mode is changed. T1.6.4 and F1.6.1 and F1.6.2 are changed. F1.18.4 is changed. F1.18.6 is changed. F1.18.7 is changed. Standard Serial I/O Mode is changed. Table of Contents is changed. T1.1.1 is changed. T1.1.2 is changed. F1.1.2 is changed. F1.1.3 is changed. T1.1.3 is changed. F1.2.1 is changed. Text is changed. T1.6.1 is delated. Text is changed. T1.6.4 and F1.6.2 are delated. Table name of T1.6.3 is added. T1.7.1 is changed. F1.7.1 is changed. Text is changed. F1.7.6 is changed. Text is changed. Text is changed. T1.7.4 is changed. Text is changed. T1.7.7, F1.7.9 and text are delated. Text is changed. F1.9.1 is changed. Text is changed (NMI Interrupt is delated.) T1.9.1 is changed. T1.9.5 is changed. F.1.9.8 is changed. F.1.9.9 is changed. Text is delated (NMI Interrupt is delated.) Text is delated (NMI Interrupt is delated.) F.1.12.4 is changed. Text is changed. F.1.18.3 is changed. T.1.18.1 is changed. F.1.18.10 is changed. T.1.19.1 is changed. T.1.19.2 is changed. Deletion of a voltage desplay of a header. Deletion of a voltage desplay of a header. Deletion of a voltage desplay of a header.
2.01 Oct 27, 2003
3.00 Jul 22, 2004
A- 3
Rev.
Date Page P153 P154 155 P156 P157 P163 P167 P168 P169 P170 P180 P181 P183 P184
Description Summary T.1.19.6 is changed. Deletion of a voltage desplay of a header. T.1.19.7 is changed. Deletion of a voltage desplay of a header. Deletion of a voltage desplay of a header. Deletion of a voltage desplay of a header. T.1.19.15 is changed. T.1.20.3 is changed. T.1.21.2 is changed. T.1.21.3 is changed. T.1.21.4 is changed. Text is changed. IT800AFE (Analog Front End) is added. F.1.23.2 is changed. Text is changed. T.1.23.2 is changed. F.1.23.4 is changed. Words standardized (On-chip Oscillator). T.1.1.3 addition and changed. L11-L12 addition and changed. L2-L5 addition and delated. T.1.7.6 part of delated. L19 is delated. Text is changed. F.1.1.2 is changed. T.1.1.3 and F.1.1.3 are added. T.1.1.4 is changed. F.1.9.6 is changed. F.1.9.7 is changed. Text is changed. F.1.9.11 is changed. Text is changed. F.1.10.1 is changed. F.1.12.1 is changed. F.1.12.2 is changed. T.1.12.3 is changed. F.1.12.8 is changed. P86 is added. T.1.12.5 is changed. F.1.13.1 is changed. F.1.13.2 is changed. F.1.13.5 is changed. L1-L13 are added. L5-L8 are added. L1-L11 are added.
3.00 Jul 22, 2004
3.01 Feb 17, 2005
P7 P34 P38 P42 P157
4.00 Aug 05, 2005
P1 P5 P7 P56 P57 P61 P66 P77 P78 P84 P85 P86 P88 P93 P94 P97 P105 P106 P108
A- 4
Rev.
Date Page P110 P114 P116 P118 P119 P121 P123 P130 P137 P147 P151 P160 P165 P176 P190 T.1.15.2 is changed. L1-L11 are added. L1-L10 are added. F.1.16.1 is changed. T.1.16.2 is changed. T.1.16.4 is changed. L8-L16 are added. Text is changed.
Description Summary
4.00 Aug 05, 2005
L2, L5-L6 and L12 are changed. Note is added. T.1.19.3 is changed. T.1.20.1 is changed. L12-L13 are added. T.1.21.4 is changed.
P188 to Appendix is added.
A- 5
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
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1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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(c) 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
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